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Intel 15th Gen Arrow Lake CPU Layout Leaks Out: The Mixing of P and E Cores

For gamers and enthusiasts, the "true" Core Ultra processors will launch later this year in the form of the 15th Gen Arrow Lake family

Intel’s 1st Gen Core Ultra processors had a moderate to lukewarm release. Underwhelming performance, marginal efficiency improvements, and limited availability make it seem like a test drive for the 4nm-class Intel 4 process node. For gamers and enthusiasts, the “true” Core Ultra processors will launch later this year in the form of the 15th Gen Arrow Lake family. We already know the basic details of these chips, including process nodes, core architecture, and packaging. Today’s leak reveals the layout of the CPU die. [Source: Xino]

Thanks to Kepler for dissecting the below annotation

The Arrow Lake CPU tile has undergone a fraternization of sorts. With Alder, Raptor, and Meteor Lake, the P and E-core clusters are grouped separately (below). Arrow Lake spreads the quad-cluster pairs of Skymont (E) cores between columns of Lion Cove (P) cores.

Source: WikiChip

It’s unclear why Intel has scattered the E-core quads between the P-cores, but it likely pertains to inter-core or memory latency. The 12th and 13th Gen processors suffer from high E-core latency. The E-cores connect through the L2 cache clusters using the L3 cache ringbus and vice versa. This adds up to inefficient figures for the outer cores. Placing the E-core clusters further apart seems counterproductive, but I suppose we’ll see.

Previous coverage on Arrow Lake:

Areej Syed

Processors, PC gaming, and the past. I have been writing about computer hardware for over seven years with more than 5000 published articles. Started off during engineering college and haven't stopped since. Mass Effect, Dragon Age, Divinity, Torment, Baldur's Gate and so much more... Contact: areejs12@hardwaretimes.com.
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