The specifications of AMD’s Zen 5 mobile flagship have leaked out. Strix Halo will power some of the fastest gaming laptops, with a console-level GPU. This chiplet-based processor will feature two Zen 5 CCDs, each packing 8 cores and a Graphics Compute Die (GCD) with a potent RDNA 3.5 GPU. This will be the first Ryzen APU with a separate iGPU die. Intel adopted this strategy with its Meteor Lake (and Arrow Lake) processors wherein the CPU, GPU, and IO are placed on disaggregated tiles.
Strix Halo, AMD’s Zen 5 mobile flagship, will feature 16x Zen 5 cores and 64MB of L3 cache (32MB x2). This implies that the CCDs (CPU dies) are the same as the desktop variants. The monolithic mobility dies feature half the L3 cache, 16MB per die. However, they are still different from Granite Ridge, or so the rumor claims.
The GPU features 40 RDNA 3.5 Compute Units, or 2560 shaders (stream processors) clocked between 2-3GHz, and backed by 32MB of Infinity Cache. This is the first time a large L3 cache is included on an integrated mobile GPU.
Strix Halo will feature a potent NPU based on the XDNA 2 architecture. The NPU on Strix Point is allegedly capable of delivering 45 TOPs so we can expect at least 75-80 TOPs from this behemoth. The processor should easily deliver ~100 TOPs of AI performance with the CPU and GPU included.
The Strix Halo processors will feature a complex 16-channel LPDDR5 memory, each 16-bit wide. You can read more about LPDDR5 and how it differs from DDR5 here. The 32MB L3 cache and the 16-ch memory controllers should keep the 40 CU RDNA 3.5 GPU fed.
There’s not much new info on Strix Point or Granite Ridge. As reported in our Zen 5 brief, the Ryzen 9000 desktop processors will feature 16x Zen 5 cores (32 threads) across two 4nm (TSMC N4) dies. The IO logic will be housed on a 6nm (TSMC N6) die similar to Raphael. The iGPU will feature 2x RDNA 3 CUs and the SoC will offer 28 PCIe Gen 5 lanes. Granite won’t include an NPU unit.
- 45-75W->
- Strix Halo (chiplet-based H): 16x Zen 5 on TSMC N4P: FP11.
- GPU: 40x RDNA 3.5 CUs + 32MB MALL.
- L2 Cache: 16MB (1MB per core).
- L3 Cache: 64MB (32MBx2).
- NPU: 75T?
- Strix Halo (chiplet-based H): 16x Zen 5 on TSMC N4P: FP11.
- 15-54W->
- Strix Point (hybrid, monolithic U/H): 4x Zen 5 + 8x Zen 5c on TSMC N4P: FP8.
- GPU: 16x RDNA 3.5 CUs.
- L2 Cache: 12MB (1MB per core).
- L3 Cache: 24 MB (16MB + 8MB).
- NPU: 45T?
- Kraken Point (hybrid, monolithic U/H): 4x Zen 5 + 4x Zen 5c on TSMC N4P: FP8.
- GPU: 8x RDNA 3.5 CUs.
- NPU: 45T?
- Strix Point (hybrid, monolithic U/H): 4x Zen 5 + 8x Zen 5c on TSMC N4P: FP8.
Strix Point, the mainstream Zen 5 mobile lineup will feature 12 cores (4x Zen 5 and 8x Zen 5c). These will allegedly be placed on the same (4nm) die but on different CCXs. They will share 24MB of L3 cache divided into 16MB and 8MB chunks. The NPU will be rated at 45 TOPs, and memory support will include DDR5 and LPDDR5. Strix Point will feature 12 core (4P + 8E) and 10 core (4P + 6E?) SKUs, with up to 16 CU RDNA 3.5 GPUs clocked at 2.6-2.7GHz. It’ll also feature 16 PCIe Gen 4 lanes for a discrete GPU.
Kraken Point will be a stripped-down version of Strix Point. It will offer up to 8 cores (4x Zen 5 + 4x Zen 5c) and 16MB of L3 cache. The NPU will be on par with Strix (45 TOPs), with similar memory controllers. Lastly, the iGPU will be half as wide, consisting of 8 RDNA 3.5 CUs, but retaining the 16 PCIe Gen 4 lanes.
Fire Range is similar to Strix Halo, but lacks the iGPU die, using the integrated 2 CU RDNA 3 solution. It is likely meant to be paired with discrete graphics processors, and trades on-board GPU prowess for more PCIe lanes (28 Gen 4?), a 3D V-Cache variant with 128MB of L3, and wider DDR5 channels. Like Granite, it lacks an NPU block.
Via: Golden Pig Upgrade.
