AMD Ryzen 9000 Series Specs and Release Date: Everything We Know About Zen 5

AMD has officially confirmed that its Zen 5 chips and the corresponding Ryzen 9000 processors will launch in the second half of 2024

AMD’s next-gen Ryzen 9000 processors are on track for launch in the second half of this year. We know a lot about the specifications, architecture, and release date of the Zen 5 CPUs. In this post, we’ll break down everything we know about the next-gen Ryzen 9000 series processors. First, we’ll review the expected release date, followed by the CPU specs and core architecture.

AMD Ryzen 9000 Series Release Date

AMD has officially confirmed that its Zen 5 chips and the corresponding Ryzen 9000 processors will launch in the second half of 2024. This falls in line with what was reported last month. The chipmaker’s official roadmap says the same, there’s no reason to doubt it. But, when exactly in the second half of 2024 will the Ryzen 9000 series launch?

Looking back at AMD’s previous launches, the Ryzen 5000 CPUs were launched in October 2020, while the Ryzen 7000 series landed in September 2022. Both lineups were announced at the preceding Computex events, followed by a retail launch in the fall. Therefore, it would be fair to say that the Ryzen 9000 processors will be announced at Computex in June. The launch should take place between August and November. According to rumors, the Zen 5 chips are already in mass production.

AMD Ryzen 9000 “Granite Ridge” Specs: The Zen 5 Core

Every leak points to a 16-core flagship for the Ryzen 9000 desktop lineup consisting of two 8-core CCDs, each packing 32MB of unified L3 cache. The Zen 5 chips will be fabbed on TSMC’s 4nm or 3nm process node. Considering the (relatively) early launch schedule, however, I’m willing to bet that it’ll be the former rather than the latter. And AMD generally tends to shrink nodes after every two generations.

Zen 5 Front End

The Zen 5 core architecture (codenamed Nirvana) will be a major upgrade over Zen 4, with a reworked frontend and a wider backend. Starting from the top, the L1I data cache has been increased from 32KB to 48KB (12-way), complemented by an expanded Data Translation Buffer and a recalibrated branch predictor.

AMD Ryzen 9000 Zen 5
Source: Moore’s Law is Dead

In out-of-order CPUs, the branch predictor is one of the most important components. Sitting at the top of the pipeline, it controls the instruction flow along with the Branch Target Buffer (BTB), which has also been upgraded. Zen 5’s branch predictor executes “Zero bubble” conditional branches. This implies that conditional branches are taken without interrupting or stalling the pipeline.

The decoder looks unchanged (4-way) with a 2-basic block fetch. The rename/dispatch buffer has been consolidated to simultaneously process up to 8 micro-ops (previously 6) with support for op-fusion. This allows two micro-ops from the same instruction to be treated as one at some points in the pipeline, doubling the effective throughput.

Zen 5 Backend

Zen 4

Zen 5 strengthens AMD’s already formidable Integer Execution. The integer scheduler has been reinforced into a unified queue with “larger structure sizes.” This simply means that the multiple smaller scheduler windows have been consolidated into larger queues (4->2). The integer ALU count has been increased to 6 (previously 4) to accommodate the higher throughput.

A fourth AGU (Address Generation Unit) has also been added to properly feed the load-store queues. Overall, we’ve got 10 execution ports on Zen 5’s Integer backend. The Load/Store bandwidth has been expanded to 4 loads (previously 3) or two stores per cycle.

Via: InstLatX64

On the Floating Point end, all four execution ports have been doubled in width to 512-bit to support AVX-512 instructions. A fifth port consisting of two 256-bit units has also been added. The expanded EUs mean larger floating point registers to sustain them, substantially larger. For comparison, Intel designs only consist of one or two 512-bit units per core.

Ladder L3 Fabric and Infinity Fabric Gen 3

AMD’s Ryzen 8000 processors will use an upgraded core interconnect known as the Ladder L3 Fabric (originally leaked by AdoredTV). This is related to the 3rd Gen Infinity Fabric, which will act as the die interconnects for AMD’s next generation of chiplet products. This bus impacts the core-to-core latency and bandwidth, which is crucial in gaming workloads. MLID claims that the fabric will be clocked at 2400MHz with a memory target of DDR5-8000 using EXPO.

AM5 800 Series Motherboards

AMD is working on an 800-series chipset for Zen 5 that will launch ahead of the Ryzen 9000 processors. The flagship X870E chipset will feature two Promontory 21 chips and an ASM4242 USB 4 controller. The inclusion of up to 20 PCIe 5 lanes (for dGPU and NVMe) will be the highlight. The B850 chipset will be the core of AMD’s next-gen budget offerings. It will sport PCIe Gen 5 support for at least the dGPU slot (x8 or x16?).

A B840 chipset based on Promontory 19 is also planned, but details remain sparse. AMD has set a memory target of DDR5-8000 for the Ryzen 9000 CPUs (with EXPO profiles), with an Fclk target of 2400MHz. The latter shouldn’t be an issue as the Ryzen 8000G processors are already designed for fabric clocks of 2400MHz and higher.

AMD Ryzen 9000X3D and Zen 5 V-Cache

According to Kepler, the Ryzen 9000X3D processors (Zen 5 3D V-Cache) will be revealed during CES 2025, slated to be held in the first week of January 2025. If the Ryzen 9000 “Zen 5” CPUs launch between summer and fall (June to September), then a 6-month gap separating them from the 3D V-Cache variants makes sense. This will depend on when Intel launches its 15th Gen Arrow Lake processors. They’ll have a similar effect on the market as Raptor Lake.

Areej Syed

Processors, PC gaming, and the past. I have been writing about computer hardware for over seven years with more than 5000 published articles. Started off during engineering college and haven't stopped since. Mass Effect, Dragon Age, Divinity, Torment, Baldur's Gate and so much more... Contact: areejs12@hardwaretimes.com.
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