At the Intel Innovation Event today, the chipmaker unveiled its second Xeon “Sierra Forest” processor for cloud providers. Leveraging up to 288 cores (XCC), it will launch alongside the more marketed 144-core variant. Unlike traditional Xeon Scalable chips, Sierra Forest will leverage the denser, more power-efficient “Sierra Glen” E-core architecture. This is essentially Crestmont with some cloud-specific optimizations, such as support for advanced instructions missing on the client design.
The Xeon Sierra Forest family will leverage up to five chiplets (or tiles), including an interposer, two compute tiles, and two I/O tiles. The I/O dies will be identical to the ones on Granite Rapids, as will be the process node of the compute dies: Intel 3, an enhanced version of Intel 4 with high-performance libraries.
Each of the compute tiles on Sierra Forest will consist of 36 “Sierra Glen” clusters paired with 108MB of shared L3 cache and 6-channel DDR5 memory support. Like Gracemont and Crestmont, the Sierra Glen cores exist in clusters of four with 4MB local L2 cache and 3MB of L3 cache that is pooled with the other clusters. A single tile adds up to 144 cores, while two make up the XCC variant with 288 cores.
The Xeon Sierra Forest processors will feature two I/O dies, fulfilling the duties of both the SoC and the I/O die. It consists of an x24 UPI connection for 2P servers, 68 PCIe Gen 5 lanes inter-compatible with CXL 2, and the I/O fabric. The memory controllers on these chips are placed on the compute dies (6-channel each). For the XCC variant with 288 cores, we’re looking at DDR5-6400 (ECC) 12-channel memory support out of the box.
The 6th Gen Xeon Sierra Forest processors are slated to land in the first half of 2024 in 144 and 288 core variants. Unlike its rival, it lacks hyper-threading (SMT) and will arrive nearly a year later than AMD’s Epyc Bergamo lineup, which features up to 128 “Zen 4c” cores and 256 threads, with support for SMT, AVX512, and all other advanced instructions available with stock Zen 4.