CPUsNews

Intel Sapphire Rapids-SP Cache Hierarchy Revealed by Leaked Benchmark

Intel’s Golden Cove core architecture is slated to launch with the Alder Lake hybrid processors towards the end of the year. While both Tiger Lake and Rocket Lake featured derivatives of Sunny Cove (Willow and Cypress), Golden Cove will be a major upgrade with an expected IPC gain of 20-25% over existing designs. Based on the 10nm ESF node, it will power all of Intel’s next-gen platforms from Alder Lake to Sapphire Rapids. As with most new core designs, we should see the L1 and L2 caches grow or at least undergo some sort of optimization.

The cache configuration of Golden Cove was leaked a few months back via a Linux patch, and while the low-level cache is generally identical across platforms, the L3 cache generally tends to be larger on server and HEDT platforms. The same appears to be true for Sapphire Rapids.

uArchGolden CoveWillow CoveGracemontTremont
L1 Data48 KiB
/12-way
48 KiB
/12-way
32 KiB
/8-way
32 KiB
/8-way
L1 Inst32 KiB
/8-way
32 KiB
/12-way
64 KiB
/8-way
32 KiB
/8-way
L21.25 MiB
/10-way
1.25 MiB
/20-way
2 MiB
/16-way
(per Module)
1.5-4.5 MiB
/12-way
(per Module)
L312 MiB
/12-way
(3 MiB per Core)
12 MiB
/12-way
(3 MiB per Core)
12 MiB
/12-way
(3 MiB per Module)
4 MiB
/16-way

The L1 Data and Instruction caches appear to be identical to Alder Lake at 48KB and 32KB, respectively but the L2 cache is quite a bit larger at 2MB (vs 1.25MB on Alder and Tiger Lake). The L3 cache is also nearly 4MB per core on Sapphire Rapids, while Alder Lake and Tiger Lake are both limited to 3MB per core.

Sapphire Rapids is said to be based on a tile-based (chiplet/MCM) design which is one of the reasons the high-level cache has been beefed up. We should see 2-4 tiles on the higher-end designs with a maximum core count of 56-60 per socket.

Source: Benchleaks

Areej

Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started my first technology blog, Techquila while in college to address my hardware passion. Although largely successful, it was a classic example of too many people trying out multiple different things but getting nothing done. Left in late 2019 and been working on Hardware Times ever since.
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