The specifications of Intel’s 15th Gen Arrow Lake processors and the PCH (Platform Controller Hub) have surfaced. While we already know much about the CPU architecture, the PCH (chipset) has been a mystery. Starting from the top, Arrow Lake-S is listed as having 24 (8P + 16E) cores. This is a pre-alpha sample, but hyper-threading appears to have been disabled from the BIOS, limiting the thread count to 24 (8P +16E). We’ve previously covered Intel’s upcoming shift from hyper-threading to Rentable Units. Arrow Lake will feature neither.
Source: YuuKi_AnS.
The CPU has a base (PL1) TDP of 125W, and a 3.5GHz clock has been listed as either the P-core base clock or the E-core boost. Since this is a pre-alpha sample, the frequencies will be lower than the final market values. The P-cores codenamed “Lion Cove” are expected to feature 3MB of L2 cache (50% more than Raptor Lake: 2MB) and a <5% IPC uplift. Combined with the “Skymont” E-cores, these processors should offer a 15% multi-threaded performance improvement over Raptor Lake.
The Arrow Lake-S family will debut alongside the LGA1851 socket. The accompanying Z890 chipset indicates the existence of two more dies with 14 (6P + 8E) and 22 (6P + 16E) cores. The CPUs natively support DDR5-6400 memory (up from DDR5-5600), with 20 PCIe Gen 5 lanes (dGPU + M.2 NVMe), and four Gen 4 lanes for an M.2 SSD. Up to 8 SATA III lanes, two USB 4.0, and one Thunderbolt 4 port are also included.
On the PCH, we’re looking at a DMI3 x8 (Gen 4) interconnect to the CPU, 24 PCIe Gen 4 lanes, 8 SATA III ports, 10 USB 3.2 Gen 2×1, Bluetooth 6/WiFi 7, and 14 USB 2.0 ports.
Intel’s 15th Gen Arrow Lake processors are on track to launch in the second half of this year. They’ll be the first to leverage the Intel 20A node, featuring RibbonFET (GAA) and backside power delivery.
Our previous coverage of Arrow Lake:
