Some interesting bits about AMD’s next-gen processors have surfaced. The Zen 5 core, codenamed Nirvana, will be a major rework of the Zen microarchitecture, featuring a wider front end, larger cache buffers, and a faster interconnect. Zen 5 will power the Ryzen 8000 “Granite Ridge” and Fire Range client processors and the Epyc “Turin” data center processors. The top-end Epyc configuration will comprise 16 CCDs, packing 128 cores and 256 threads alongside 512 MB of L3 cache.
The Zen 5 CCD is codenamed Eldora and will retain the 8-core per-die structure introduced with Zen 3, packing 32MB of L3 cache alongside. The 3D V-Cache variant of Turn (Turin-X) will feature 1.5GB of L3 cache stacked atop 16 Zen 5 CCDs.
The Turin Dense variants will integrate up to 192 Zen 5c cores and 256 threads. The L3 cache on the top-end parts will come up to 384MB, spread across 12 tightly packed CCDs. The Turin data center processors will have a TDP rating of up to 500W, roughly 100W more than existing Epyc Genoa offerings.
