AMD’s Ryzen 7000 CPUs, leveraging the Zen 4 cores, didn’t alter the microarchitecture (the core building blocks) much. The core counts have remained the same since Zen 2, and the cache and CCD structure hasn’t changed since Zen 3, either. The frontend and backend are also largely the same, with some minor increases to the cache and register buffers, and that’s just about it.
Things should shake up quite a bit with Zen 5, which is expected to be the most extensive overhaul since Zen 2. Officially, the Zen 5 core powering the Ryzen 8000 CPUs will feature a revamped frontend and a wider instruction issue. It’ll also come with integrated machine-learning instructions and an emphasis on efficiency.
The core counts are expected to stay the same, ranging from 6 on Ryzen 5 to 16 on the Ryzen 9 SKUs. The L2 cache will be doubled from 1MB to 2MB per core, bringing it to parity with Intel’s Raptor Cove design. The L3 cache will remain 32MB for single CCD Ryzen 5 and 7 chips and 64MB (32MB x2) for dual-CCD Ryzen 9 parts.
Looking at the Zen 4 block diagram above, you can see that the decoder is a little primitive, spitting out just 4 instructions per cycle (versus a 6-way decoder on Golden and Raptor Cove). We should see a 6-way decoder with Zen 5, a larger I-Cache (32KB>48KB), and a wider dispatch (up to 9 macro-ops per cycle?).
The backend won’t change much except the registers. The memory subsystem should get some nifty expansions. The load/store queues should get wider along with the D-Cache (32KB>48KB), and the L2 will also be doubled from 1MB to 2MB per core. Zen 4 can only do 3 (2 vector loads) or two stores per cycle with an L2 bandwidth of 32B. It has a load and store queue of 88 and 64, respectively.
Intel’s Golden and Raptor Cove cores can do 3 256-bit loads or 2 512-bit loads per cycle. The load/store queues are much wider at 192/114, and the L2/L3 bandwidth is twice as much (64B per cycle).
The other major change will come in the form of the inter-core fabric. Zen 5 will feature a unique core interconnect called Ladder L3 Fabric. In this topology, each core is directly connected to the opposite one. The adjacent cores are connected using a ladder-like common bus connected to an identical opposite bus via seven high-speed links. This topology should improve inter-core latency, bandwidth gaming performance, etc.
There have been confusing rumors about the Zen 5 process node. Multiple reports have stated that AMD has prepared the core for the TSMC N4 (4nm) and N3 (3nm) nodes. However, recently it has been disclosed by multiple sources that it will leverage the latter. The Ryzen 8000 CPUs leveraging the Zen 5 core should land in the second half of 2024, likely in Q3.