The other day a patent was discovered that used AMD’s entire Zen core architecture to explain the workings of a modern microprocessor. The problem? It was an Intel patent. The controversy was resolved with Intel releasing the following statement:
When filing a patent application, citation to existing and relevant technologies in the industry is a common practice. U.S. Pat. No. 11,294,809 discloses Intel innovations in the context of alternative implementations and does not attempt to copy or patent inventions of any other company. Intel respects the intellectual property rights of all parties.
Intel
Long story short, it was a patent quoting a competitor’s technology without trying to copy or infringe any IP. Now, a patent from AMD has surfaced that shows the frontend of a future core (maybe Zen 5?). Interestingly, it looks quite similar to Intel small cores’ frontend including Tremont and Gracemont.
Source: Wikimedia
Both core designs have dual fetch/decode windows fed by the branch predictor. The primary difference is with respect to the instruction cache. In the case of Gracemont, the instruction cache sits between the branch predictor and the decoders, feeding both concurrently. However, AMD’s patent shows the dual fetch and decode pipelines concurrently fed by instructions using a memory map instead of a branch predictor.
Another diagram shows the branch predictor feeding the two fetch/decode pipelines in tandem. The instruction cache sits between the two fetch units, feeding the fetch-decode pipeline alongside the branch predictor (concurrently).
There are two ways the fetch and decode pipelines are fed using the BP. Using two independent streams of instructions or using a branch window that smartly feeds the fetch window depending on the utilization of each fetch pipeline.
A reorder module has been placed in the frontend, right below the decoders to reorder the decoded instructions which is a major departure from standard CPU pipelines.
A similar patent demonstrates another possible way to widen the frontend. Two op-cache streams are used to feed the dispatch queue (to the backend) instead of one to keep it filled. The frontend is generally the bottleneck in most CPU architectures, and if AMD can alleviate this with its next-gen (Zen 5?) designs, it’ll win the chipmaker many laurels.
Via: 0x22h
