Intel’s next-gen Ocean Cove core looks almost identical to AMD’s 1st Gen Zen core…going by a new patent. Ocean Cove is expected to power the 14th Gen Meteor Lake/Arrow Lake processors which will be Intel’s first chiplet design. Zen, on the other hand, was Team Red’s first modular architecture, launched back in 2017. It’s important to remember that this is a mere patent and the final core blueprint will be drastically different. As such, this may be a sheerly experimental design.
There are striking similarities between Ocean Cove and Zen 1, to the point that it makes me think it’s a mockup rather than even an early blueprint. Even the instruction cache and the decode bandwidth are the exact same. The segmentation of the backend into the integer and floating-point execution units, as well as the memory subsystem bandwidth, are identical as well.
The fetch unit is also a carbon copy with a decoupled (Hash Perceptron) branch predictor, 32B fetch/decode bandwidth, and a 64K ICache.
The decode engine also is pretty much the same on both sides with a four-way decoder plus op-cache and a six-way dispatch.
The Integer Execution features six ports, including four ALUs and two AGUs fed by 6 uops per cycle from the dispatch. These are paired with a 192-entry register file and low-level cache.
Similarly, the FP EUs are also identical on both ends with a 192-entry ROB, 128-bit loads, and a 160 entry physical register file used for INT to FP, or FP to INT conversions. This reduction in the ROB (from 512 to 192) is highly unlikely making it seem all the more impractical and unlikely.
The load/store bandwidth and the cache hierarchy are also a regression from Golden Cove, making it an improbable design.
The absolute similarity between the two core architectures shows that Intel is highly interested in AMD’s modular approach. However, you can be sure that we’re not gonna see something too similar to Zen 3/Zen 4 with Ocean Cove or its predecessor.
The difference in AMD and Intel’s SMT implementation and the CCD (chiplet/die) layout are further proof of this.
Update: According to Ian Cutress this isn’t really a patent. Rather it’s a summer project from an intern that explains how a CPU works.
