Additional details regarding AMD’s first big.LITTLE design, otherwise known as a heterogeneous or hybrid core architecture have surfaced via a patent filed by the company. The patent explains the kind of approach the company plans to take with its first hybrid-core processor, codenamed Strix Point. We already know from previous leaks that Strix Point will leverage Zen 5 as the high-performance (big-cores) and Zen 4D as the low-power cores (low-power). The processors will be based on TSMC’s N3 (3nm) process and launch sometime between 2023-24, likely with integrated graphics and an L4 cache shared between the two core clusters.
As you can see in the above image from the patent, the big cores will sit within a standard CCX (core complex) of eight cores while the little cores will use a separate die. The two will be connected using the Infinity Fabric and the L4 cache. The two chiplets will feature a common I/O and memory controller die also connected via the Fabric. This means that we might see the Zen 4D chiplet fabbed on TSMC’s N5 (5nm) or 4nm (N4) process and the Zen 5 chiplet fabbed on the N3 (3nm) node, with the I/O die using the 7nm or a more mature node. The integrated GPU should use yet another chiplet or will be coupled with the I/O die. There’s no mention of 3D stacking or V-Cache technology, but considering the sheer number of dies involved it’s very possible that we’ll see a separate cache die stacked on top of the big cores.
The below flowchart shows the workload distribution between the two core clusters. It would seem that if the utilization metrics of a task exceeds a certain threshold, it will be conferred to the big cores, otherwise handled by the small cores. In the case of the former, the little core will save its state into the cache/memory and be placed in an idle/stall state, much like how SMT does it. However, it will more complex, considering that the two core clusters are on different dies.