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AMD Zen 4 Ryzen CPU Pad Design Leaks Out: DDR5, 28 PCIe 4.0 Lanes and up to 170W TDP

Thanks to @ExecFix, we now have a rough mockup of the pin layout of AMD’s Zen 4 based Ryzen 6000 (Raphael) processors which will move from the PGA-based AM4 socket to the LGA-based AM5. While we only know the basics of the next-gen Ryzen CPUs, it’s almost certain that they will be based on TSMC’s 5nm EUV process with a core count exceeding 16 and a TDP of 120W for the X variants. A special SKU, most likely the one with more than 16 cores will push the TDP to 170W.

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In addition to this, the PCIe lane count will be increased from 24 to 28, although the PCIe 4.0 standard will be retained. Unlike Intel’s Alder Lake-S CPUs which will support both DDR4 and DDR5, Raphael will be limited to DDR5, most likely on account of performance reasons. It’ll be interesting to see whether AMD once again changes the CCD and cache layout or stick to the octa-core CCX design. It’s also rumored that starting with Raphael, all AMD CPUs will come with an integrated graphics die (RDNA 2+) to counter Intel’s primary advantage in the OEM market. This has yet to be confirmed and if it turns out to be true, it’ll be a major change for the Red platform.

Areej

Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started my first technology blog, Techquila while in college to address my hardware passion. Although largely successful, it was a classic example of too many people trying out multiple different things but getting nothing done. Left in late 2019 and been working on Hardware Times ever since.
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