According to a well-reputed source (Greymon, Twitter) on AMD’s processors, the chipmaker will be using a mix of 5nm and 3nm dies for its next to next-gen CPUs and GPUs. The leaker claims that the Radeon RX 8000 series (RDNA 4) will use a chiplet design with some of the dies fabbed on TSMC’s cutting edge 3nm and the rest on the 5nm node. The GCDs (compute dies) will likely leverage the 3nm process while the I/O die, and perhaps the cache die will use the relatively older process.
RDNA 4 is likely to be a full-fledged MCM (chiplet) design with several dies powering the GPUs, all based on the same microarchitecture but different process nodes. We should see separate heterogeneous dies for compute, I/O, and L3 cache on the same substrate, possibly 3D stacked on one another. RDNA 3, on the other hand, will feature a chiplet design only for the higher-end GPUs and without a separate I/O die. (Xanax) We should see two or more compute dies and an active bridge connecting them with the L3 cache.
As for the Zen 5 hybrid core APU, we’re looking at 3nm compute dies featuring Zen 4D (efficiency cores) and Zen 5 CCDs (performance cores), with the former likely 3D stacked on the latter. The I/O die will be fabbed on the 5nm node, down from 7nm for Raphael/Genoa. Strix Point will be AMD’s first hybrid processor, a direct response to Alder Lake and Raptor Lake, with powerful integrated graphics and advanced 3D packaging.
AMD’s approach to hybrid core CPUs should be slightly different from Intel’s. We may see an L4 cache acting as the last level cache for both the core clusters. The software and the memory controller won’t “see” the LLC and therefore, it won’t require any kind of optimization from developers. Generally, it shouldn’t require any coherency hardware, but that may change depending on how AMD decides to implement it. Of course, this will require extra die size but looking at modern packaging technologies, it might be stacked above regular compute dies. Strix Point is slated to launch sometime in late 2024/early 2025.