AMD is getting ready to launch its first hybrid core processor in the form of Phoenix 2 later this year. The chipmaker’s latest “Processor Programming Reference” mentions the use of “Performance” and “Efficiency” cores, including architectural feature differentiation such as microarchitectural resources. Consequently, we’re looking at different performance, clocks, and power targets for the different core types.
#AMD in the Phoenix1 Processor Programming Reference (PPR) uses the same phraseology for the big and little cores as #Intel https://www.amd.com/system/files/TechDocs/57019-A0-PUB_3.00.zip
Interestingly, there’s no mention of Zen 4c cores. AMD has included data bits for a heterogeneous core design, but this doesn’t necessarily mean we’ll see two different cores. There’s a good chance that we’re looking at a downclocked core cluster. However, considering that the mobile Ryzen processors all feature cut-down L3 caches, which is what Zen 4c does as well.