AMD’s chiplet-based Instinct MI200 data-center accelerator will reportedly feature two compute dies with a total of 224 Compute Units. Each of the compute dies on the chip codenamed “Aldebaran” will feature 128 Compute Units across 8 Shader Engines, but 16 of them will be disabled to improve yields (one on each SE). This means that overall 32 Compute Units will be disabled across the two dies, resulting in a CU count of 224 (down from 256).
Furthermore, it’s being speculated that the MI200 will be based on TSMC’s 5nm EUV process, making it the first AMD and non-Apple product to leverage the advanced node. Till now, only Apple’s M1 and A14 SoCs have been fabbed on TSMC’s 5nm node on a commercial level.
This is still just sheer speculation as the MI100 uses the N7 process and migrating it to N5 will require a fair bit of additional work while also making the SKU more expensive. Considering the rate at which TSMC’s N5 production has been progressing, however, it’s not completely unimaginable.