The graphics card market is going to get a whole lot more competitive in the coming years as chipmakers exploit every technology to push Moore’s Law to its limits. Starting with the adoption of chiplets for the RDNA 3-based Radeon RX 7900 XT/7800 XT GPUs, all three teams are keen on loading more and more SRAM onto their designs. AMD was the first to integrate a large L3 “Infinity” cache into its RDNA 2 architecture, and much like the chiplet route, its rivals are going to follow suit.
I'm not 100% sure because each different Intel team has a different name for the cache (L3 vs L4 for example) but it seems to be 112MB.
The recent NVIDIA data breach has already confirmed this. All the next-gen Ada Lovelace GPUs will pack a fat L2 cache, led by the AD102 and its 96MB L2 cache reserves. This is a massive increase over the 6MB of L2 cache housed by Ampere and Turing cores. What’s interesting though, is that while AMD has added a large third layer of cache to its RDNA 2 GPUs, both NVIDIA and Intel are consolidating the existing L2 banks.
GA102 (Ampere)
According to @Kepler_L2, the 3rd Gen Arc Battlemage GPUs will also integrate a large L2 cache (up to 112MB), normalizing the use of massive SRAM banks in graphics processors. It’s unclear whether Battlemage will feature a chiplet design as well, but it’ll be absolutely necessary if Intel wants to compete in the high-end PC gaming and enthusiast segments.
Processors, PC gaming, and the past. I have written about computer hardware for over seven years with over 5000 published articles. I started during engineering college and haven't stopped since. On the side, I play RPGs like Baldur's Gate, Dragon Age, Mass Effect, Divinity, and Fallout. Contact: areejs12@hardwaretimes.com.
