The Xbox Series X die has been examined by the talented Locuza, giving us a deeper idea of the SKU powering the next-gen console, and how it differs from the AMD Renoir APU. For starters, unlike the PS5 (which seems to have cut-down FPU registers), the Series X appears to have a CPU design identical to Renoir, featuring all the necessary logic and registers:
As you can see, the core complexes on the Series X and Renoir die seem more or less identical. The Execution Units and the registers appear to be of the same size without any reductions, unlike the PS5 where the Floating Point (FPU) register was cut in half. While that doesn’t necessarily affect the FP capabilities of the CPU, it does result in increased cache fetches, latency, and pipeline stalls in extreme cases.
The other interesting bit is with respect to the memory configuration. The Series X features 16GB of GDDR6 memory, with a bandwidth of 560GB/s for the first 10GB, and a much lower (of 336GB/s) if the system needs the remaining 6GB.
This is how it works: There are six 2GB memory modules connected to the SoC and four 1GB ones. This can work in two different ways, with each die mapped to the SoC via a 16×2 bit memory controller, resulting in an overall bus width of 320-bit and therefore a peak memory bandwidth of 560GB/s. However, since some of the packages are 1GB modules, this means that every 32-bit controller can access only 1GB per connection. Something similar to this is done in graphics cards to configure hybrid bus configurations such as 192-bit or 160-bit (clamshell mode) by connecting multiple chips to a single controller which results in the sharing of bandwidth between them.
I’m not sure whether MS is simply using six 2GB modules or multiple chips, but the 2GB is partitioned and the remainder of the 1GB memory is accessed via a secondary memory interface. Since there are only six 2GB chips (16×2 bits x 6), this results in a lower bandwidth of 336GB/s for the remaining 6GB.
Lastly, there’s the question of the die size. As per Locuza, the Series X SoC has a chip area of 360.45mm2 while the Series S has an area of 196.106mm2. That’s nearly the same as the official quotes.
Is it RDNA 2 or 1.1?
A little bit on this. As pointed out by multiple people, it’s impossible to say for sure but it certainly seems like the Series X is a newer design than the PS5. The Series X|S feature the newer ROP+ design (more on that here) with fewer but more efficient units (4 color ROPs on the XSX and RDNA 2 vs 8 on the PS5 and RDNA1). The stencil ROP count is the same on both at 18. Lastly, the CU design is once again closer to RDNA 1/1.1m with two sub-arrays, similar to the PS5 and RDNA 1. RDNA 2 designs have only one sub-array for all WGPs/DCUs.
