TSMC is undoubtedly the leading chip foundry in the world right now. All the latest cutting-edge silicon is based on its 7nm node. Apple, AMD, and Huawei are all using it in their latest devices. At the IEEE IEDM Conference today, TSMC revealed the next milestone in its process technologies.
The results for the initial testing of the 5nm EUV process are out, with average yields of 80%. This may sound like a lot but the test chip used is only a fraction of a modern processor.
According to TSMC, the new 5nm EUV node allows an increase of up to 1.84x in logic density. This means a reduction in the TDP by up to 30%. This will be the next logical upgrade for clients using TSMC’s 7nm process. AMD’s Ryzen 5000 (based on Zen 4) will most likely be one of the top candidates to leverage the 5nm EUV process.
The test chip in question includes 30% SRAM (cache, registers), 60% Logic (CPU) and 10% I/O (ports, PCIe). A 256 Mbit SRAM cell, at 21000 nm2, gives a die area of 5.376 mm2. If the SRAM is 30% of the chip, then the whole chip should be around 17.92 mm2.
So, if the average yield for this ~18 mm2 is about 80%, a 300 mm wafer with the same die should produce 2602 good dies out of a total 3252 per wafer (by extrapolation).
As with Intel’s 10nm Ice Lake chips, the mobile chips are usually the ones to be fabbed first on a new process. Let’s compare it to AMD’s Zen 2 chiplet. Those are 10.35×7.35mm in size. Taking the same defect rate of 1.271 per cm2, we get a yield of 41%. That’s not bad at all. Not quite ready for volume production, but shouldn’t be long before it is. Expect volume production to start by the end of 2020 with products ready for shipping by 2021 Q3-Q4.