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TSMC Working on 3D Stacked Packaging w/ 12-High Die Stacking

As process shrinking begins to hit its limits, chipmakers have started looking at other means of packing more and more transistors in a given die space. When you can’t go back or forward, you go up. That’s what 3D packaging is about. Intel recently launched its first 3D stacked SoC in the form of Lakefield, featuring both the EMIB interconnect as well as the Foveros packaging technology, encouraging other major foundries including TSMC and Samsung to hasten their efforts in the same direction.

TSMC’s primary technology that allows stacking of dies or should I say goes beyond simple chip-stacking is called SoIC: System on Integrated Chip. Unlike traditional stacking of dies using µ-bumps, it allows die-stacking by aligning and bounding the metal layers of the various silicon dies.

At the recent Technology Symposium, TSMC showed off its latest efforts in advancing this very technique. The foundry is currently testing stacking as many as 12-Hi configurations with SoIC (stacking 12 dies in one package). The dies communicate with one another using silicon vias (TSVs), and the basic plan is similar to Intel’s Foveros, only more advanced. Some layers (or dies) can be used for compute and I/O while the rest can house DRAM/SRAM or simply act as a thermal insulation layer between the active ones.

Areej

Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started my first technology blog, Techquila while in college to address my hardware passion. Although largely successful, it was a classic example of too many people trying out multiple different things but getting nothing done. Left in late 2019 and been working on Hardware Times ever since.

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