TSMC, at its annual Technology Symposium, detailed its upcoming processes, including the 5nm (NP5 and N4) and the 3nm which will be a full-fledged node. The former will be based on the 2nd Gen DUV (Deep-Ultraviolet) and EUV (Extreme-Ultraviolet) nodes, succeeding the 7nm+ process.
Then we have the “true” successor to the 7nm node, namely the N5 (5nm EUV) process which as per TSMC is progressing as per planned, with better yields than what the N7 (7nm) node had in the same stage. The foundry is already preparing the successor to N5 in the form of the form of the N5P process which will be 5% faster and 10% more power efficient than the base 5nm node.
| N7 vs 16FF+ | N7 vs N10 | N7P vs N7 | N7+ vs N7 | N5 vs N7 | N5P vs N5 | N3 vs N5 | |
|---|---|---|---|---|---|---|---|
| Power | -60% | <-40% | -10% | -15% | -30% | -10% | -25-30% |
| Performance | +30% | ? | +7% | +10% | +15% | +5% | +10-15% |
| Logic Area Reduction % (Density) | 70% | >37% | – | ~17% | 0.55x -45% (1.8x) | – | 0.58x -42% (1.7x) |
| Volume Manufacturing | Q2 2019 | Q2 2020 | 2021 | H2 2022 |
After that, TSMC is looking to introduce the N4 node which is another refinement of the N5 process, using additional EUV layers to improve density and performance. The risk production for N4 is slated for Q4 2021, followed by the volume production in 2022.
Finally, we have the 3nm (N3) node which will be the “true” successor to the 5nm process. Unlike Samsung’s 3nm node which will leverage the GAA (Gate-all-around) transistor technology, TSMC will continue to use FinFet and still achieve an impressive density gain of 1.7x. As per the foundry’s own figures, N3 will be 10-15% faster than N5 and nearly 30% more power-efficient. N3 will begin risk production in 2021 with volume production expected to start the same year as N4, in the second half of 2022.
Post 3nm and the Future: 3D Packaging and Beyond Silicon
In-line with what Intel other foundries have working on, TSMC also refreshed it’s own 3D packaging technologies. Presently, TSMC already has a wide set including Chip-on-Wafer-on-Substrate (CoWoS), Integrated Fan Out (InFO-R), Chip on Wafer (COW), and Wafer-on-Wafer (WoW). From now on, TSMC is branding all these packaging technologies as “3DFabric”.
In addition to advanced packaging techniques, TSMC is also researching alternatives to silicon to allow further miniaturization of chips. The primary candidates are nanosheets, nanowires, high mobility channels, 2D transistors, and carbon nanotubes.
