Last year, we discovered that the PS5 SoC featured a custom Floating Point Unit with fewer register files than vanilla Zen 2. The same folks have now had a deeper look at the processor powering the next-gen console to get a better idea of just deep the customizations go compared to the Zen 2 cores powering the Ryzen CPUs. Well, it turns out that while the Floating Point registers are indeed fewer, but in addition to that, the Execution Units are also smaller.
As you can see in the above shot, the standard Zen 2 core in Ryzen CPUs packs a total of x320 128-bit Floating Point register files, distributed between two evenly sized clusters. The PS5 FPU, on the other hand, has a notably smaller area dedicated to the registers. We’re looking at a reduction of a third or perhaps, a fourth compared to the original design on Zen 2. A smaller register cluster means shorter intervals before a flush which means more frequent stalls in the pipeline.
The register size of the Zen 2 grew significantly compared to the Zen 1 to account for AVX2 or 256-bit instruction support. Sony appears to have cut the Execution logic as well (nearly in half) to make up for this. It would seem that the
PS5’s FPU isn’t quite capable of native AVX256 (without breaking the instructions into two). While this does mean fewer pipeline stalls, it does somewhat limit the execution capabilities of the SoC.
Update: The 4700S shows that while the PS5 is capable of AVX256, the throughput might not be the same as Zen 2.
Plenty of modern games take advantage of AVX256, with Zen 4 even expected to support AVX512 in addition to AVX256. With that said, it’s important to remember that this conclusion is based on die-shot comparisons and isn’t a confirmation. However, seeing that the PS5 FPU is 36% smaller than the vanilla Zen 2 FPU, something has certainly been hacked off.