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RDNA 2 iGPU on AMD Ryzen 7000 APUs to Lack Infinity Cache (L3); L1 and L0 Cache Doubled

AMD’s Ryzen 7000 mobile processors (codenamed Phoenix) will retain the RDNA 2 integrated graphics architecture leveraged by the Ryzen 6000 “Rembrandt” family. However, there will be a few key changes to the memory subsystem. The L0 vector cache per Compute Unit (CU) will be doubled from 16KB to 32KB, and so will the L2. The latter will be ramped up from 128KB to 256KB per Shader Array (SA) and 512KB per Shader Engine (SE).

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 Hi Yifan,
	
 Yellow carp's cache info cannot be duplicated to GC_11_0_1.
	
 Different point to GC_11_0_1:
 TCP L1  Cache size is 32
 GL1 Data Cache size per SA is 256
	
 Others looks good to me
	
 --
 Best Regards
 Aaron Liu
Cache InfoYellow Carp (Rembrandt)Phoenix (GC 11.0.1, GFX1103)
L0 Vector Data (per CU)16KiB32KiB
L0 Scalar Inst. (per WGP)32KiB32KiB
L1 Scalar Data (per WGP)16KiB16KiB
GL1 Data (per SA)128KiB256KiB
L2 Data2048KiB (2MiB)2048KiB (2MiB)
L3 (MALL)N/AN/A

The L2 and the L1 scalar/instruction cache remain unchanged at 2MB and 16KB, respectively. There’s also no mention of an L3 or Infinity Cache (similar to Rembrandt) as seen on the Radeon RX 6000 GPUs.

The changes to the L0 and L1 caches make the Phoenix iGPU a bit of a unique case. Much like the RDNA 3 powered Radeon RX 7000 GPUs, we’re looking at a larger scalar instruction and vector cache meant to improve overall WGP performance.

 static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
 	{
 		/* TCP L1 Cache per CU */
 		.cache_size = 16,
 		.cache_level = 1,
 		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 				CRAT_CACHE_FLAGS_DATA_CACHE |
 				CRAT_CACHE_FLAGS_SIMD_CACHE),
 		.num_cu_shared = 1,
 	},
 	{
 		/* Scalar L1 Instruction Cache per SQC */
 		.cache_size = 32,
 		.cache_level = 1,
 		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 				CRAT_CACHE_FLAGS_INST_CACHE |
 				CRAT_CACHE_FLAGS_SIMD_CACHE),
 		.num_cu_shared = 2,
 	},
 	{
 		/* Scalar L1 Data Cache per SQC */
 		.cache_size = 16,
 		.cache_level = 1,
 		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 				CRAT_CACHE_FLAGS_DATA_CACHE |
 				CRAT_CACHE_FLAGS_SIMD_CACHE),
 		.num_cu_shared = 2,
 	},
 	{
 		/* GL1 Data Cache per SA */
 		.cache_size = 128,
 		.cache_level = 1,
 		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 				CRAT_CACHE_FLAGS_DATA_CACHE |
 				CRAT_CACHE_FLAGS_SIMD_CACHE),
 		.num_cu_shared = 6,
 	},
 	{
 		/* L2 Data Cache per GPU (Total Tex Cache) */
 		.cache_size = 2048,
 		.cache_level = 2,
 		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 				CRAT_CACHE_FLAGS_DATA_CACHE |
 				CRAT_CACHE_FLAGS_SIMD_CACHE),
 		.num_cu_shared = 6,
 	},
 };

Source: Coelacanth’s Dream

Areej

Computer hardware enthusiast, PC gamer, and almost an engineer. Former co-founder of Techquila (2017-2019), a fairly successful tech outlet. Been working on Hardware Times since 2019, an outlet dedicated to computer hardware and its applications.
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