Recently a rumor has been going around on the web suggesting that Big Navi based on the RDNA 2 architecture will have 24GB HBM2E memory and 5,120 shaders. I hate to say it but the leaked configuration is fake. It’s just not possible. Before I begin, let’s recall what happened the last time AMD tired to use HBM is its graphics cards. It didn’t work. There was a global shortage of units and the BOM was too high to make a decent profit out of them. Now, here’s the leaked image that was shared on Twitter:
As per this image, Big Navi will feature 80 Compute Units (or 64×80=5,120 shaders) and 24GB of HBM2E memory via a 4,096-bit bus resulting in a massive bandwidth of 2,048 GB/s. The ROP count is indicated to be 96, TMUs: 320 and 12MB of L2 cache.
Let’s talk about HBM2E. What do we know about it: The density, bandwidth and bus width. HBM2E can consist of up to eight 16Gbit dies stacked one above the other, for a total of 16GB per package. There’s also the option to use 12 chips per stack for a total of 24GB, but vendors will only keep 8-hi stacks (“There are capacitive and resistance limits as you go up the stack”). Overall, each stack will have a bus width of 1,024-bits across eight 128-bit channels. The memory frequency will stay in the 1.2GHz range resulting in a bandwidth of up to 460GB/s per stack. Consequently, a four-stack processor can reach bandwidths as high as 1.84TB/s.
(Edit: The earlier mentioned specs were that of Samsung’s HBM2E. Hynix’s offerings are more flexible. Statement from Twitter.)
Using that logic, the supposed 24GB RX 5950X should have a bus width of 1,024-bit, not 4,096. That’s the first discrepancy. The second is with respect to memory bandwidth. The leak puts the GPU bandwidth at 2,048GB/s. That’s also improbable. A single 1,024-bit stack can have a maximum bandwidth of near-about 500GB/s, not even half as much as indicated in the leak.
Just looking at the 4,096-bit width, you can tell that it’s unlikely. A bus width that high is usually paired with 64GB of memory and that kind of config won’t come to the consumer market anytime soon.
After that, there’s the ROP count. The Radeon RX 5700 XT with two shader engines and four 64-bit memory channels has a total of 64 ROPs. The rumored RX 5950XT claims 96. Unless AMD changes the Dual CU config with RDNA 2, it should be 128 ROPs.
Lastly, there’s the matter of the L2 cache. Both the Radeon RX 5700 XT and the older GCN based-Radeon VII which featured HBM2 packed 4MB of L2 cache. With RDNA, AMD has increased the size of the cache to 4MB per 40 CUs. By that logic, it should be 8MB for the 80 CU RX 5950XT. The leaked image suggests 12MB, which is again thrice as much as the 5700 XT and highly doubtful even if AMD overhauls the cache hierarchy with RDNA 2.
So, there you have it. Why the leaked GPU or whatever it is isn’t the much anticipated Big Navi or any consumer GPU for that matter. If I made any mistakes or made any false assumptions, please point them out. Cheers!