Recently, there’s been a chatter on the web regarding AMD’s Navi 2x GPUs which will be based on the RDNA 2 microarchitecture. Some of these speculations report that the Navi 2x flagship will leverage a massive 128MB of “Infinity Cache”. Till now I had my doubts, but today an AMD patent (sorry it’s a trademark, not a patent) has surfaced that describes what Infinity Cache really is. The important lines from the patent are as follows:
System-on-chip (SoC) architecture for use with central processing units (CPU) and graphics processing units (GPU), namely, SoC architecture that connects die-to-die, chip-to-chip, and socket-to-socket, used across different microprocessors to enable increased computing performance; network-on-chip, namely, technology that provides interfaces across microprocessor CPU and GPU cores, memory, hubs, and data fabric to enable microprocessor communications and increase computing performance and efficiency; microprocessor communication fabric, namely, data communication interconnect architecture responsible for collecting data, and command control interconnect architecture responsible for data sensor telemetry
AMD Patent
The Infinity Cache will be used in SoCs, namely designs with a CPU, GPU, and DRAM on the same package. The Infinity Cache will be used to improve the latency between the various dies, chips, and sockets. This makes it clear that IF won’t be used on any Navi 2x GPU including Big Navi as it’s a single-chip solution. Future GPUs with a chiplet (MCM) design, may, however, see the use of this cache to reduce the latency penalty between the various GPU dies.
The Game Cache which is basically the large L3 cache shared between the various cores of a Ryzen 3000 CPU performs the same task. They cache more and more data so that the penalty of using an MCM design is minimized.
Furthermore, looking at this patent, it sounds likely that Infinity Cache is an expanded feature of the Infinity Fabric which will likely be used in Exascale solutions with unified memory and an integrated network of CPUs and GPUs working in tandem. Remind you off something? Yes, Intel’s Aurora supercomputer works on a very similar basis with its Rambo cache and Xe Link.
Update:
GPU cores; graphics cards; video cards; video display cards; video capture cards; accelerated data processors; accelerated video processors; multimedia accelerator boards; computer accelerator board; graphics accelerators; video graphics accelerator; graphics processor subsystem, namely, microprocessor subsystems comprised of one or more microprocessors, graphics processing units (GPUs), GPU cores, and downloadable and recorded software for operating the foregoing; supercomputers; computer servers; network servers; computer workstations, namely, computers designed for advanced technical or scientific applications and high performance computing applications;
Here’s the last part of the trademark which includes GPUs. I may be wrong here, but once again, it mentions microprocessor subsystems comprised of one or more GPUs/CPUs, supercomputers, servers, network servers, etc. As such, I don’t expect IC to come to consumer GPUs anytime soon.
Many commenters have brought up adaptive caching and shared L1 caching but those are different things. These two are used to reduce cache replications across the individual core caches by reducing their address range and assigning a specific set of higher-level caches to a set of CUs, to further improve it. This doesn’t actually add any additional cache as mentioned by previous leaks on IC.
From what we know about Infinity Cache, it is an additional massive cache buffer to reduce the impact of a smaller bus. I personally believe that it’ll be utilized in future CPU/GPUs with MCM design and Exascale machines. I could be wrong here, but that also means that previous leaks about IC from RTG were utter rubbish.
More info on this by @Underfox here:
