As Moore’s Law and semiconductor miniaturization slow down, chipmakers have started investing in advanced packaging technologies. These include AMD’s 3D V-Cache (based on TSMC’s CoWoIS packaging), Intel’s Foveros (3D stacking of memory and compute logic), etc. With every successive generation, we’ll be seeing these technologies adopted in more and more complex forms. Intel’s Sapphire Rapids-SP is slated to utilize on-die HBM 2 memory in a first for the company’s server platform. Perhaps a precursor of sorts to the upcoming Ponte Vecchio super-chips.
A while back, there was a rumor that AMD would do the same with its next-gen Epyc Genoa (Zen 4) processors. However, a report from prohardver states that that won’t be the case, and AMD will position Milan-X as the rival to Sapphire Rapids-SP.
The report further alleges that while there were plans to launch one or more HBM versions of Genoa, they were discarded in favor of 3D V-Cache or Milan-X several quarters ago. The reason being that the HBM variants didn’t work well with Zen 4 as cache due to the high latency. Furthermore, no memory mapping technique worked well when the processor was paired with HBM.
The other was to use HBM as a form of directly mapped cache (read more here) using 64-byte cache lines for increase hit rates. However, this was discarded as well due to worse performance than 3D V-Cache. As a result of these failures, AMD has put the Epyc-paired HBM designs on Ice. Therefore, we’re very unlikely to see HBM versions of Milan or Genoa. 3D V-Cache, however, is about to become stable.
