Navi 3x Won’t Have a Chiplet Design, Separate Memory/IO Die Possible

There have been many rumors floating on the web claiming that AMD may use a chiplet (MCM) design with its Navi 3x GPUs (RDNA 3), two years from now. I’d like to pitch in and counter these allegations. No, AMD won’t be shifting to an MCM design with its Navi 3x GPUs, at least not yet.

Such a move can’t come in a single generation without any prior preparations. Moving to a chiplet design for a GPU is much more complex than with a CPU. Unlike the latter, GPUs have hardware dedicated to scheduling which is usually common for the entire die.

There are many ways you can approach this: Have multiple GPU pipelines, separate the graphics and compute queue as per dies, etc. However, from what we’ve seen, it looks like AMD won’t be doing any of this. Rather Navi 3x will be much more subtler change.

As per a Tweet from well-known leaker, Komachi-Ensaka, we may see a separate memory or I/O die separating the memory bus from the GPU compute die. Latency has never been an issue with GPU memory, rather it’s the bandwidth that matters. Separating the memory bus from the main GPU can help make the memory configuration more flexible, allowing for setups similar to the clamshell model.

Keep in mind that this is all speculation at this point, so take it with a grain of salt. There isn’t enough evidence indicating that AMD might even decouple the I/O or memory bus from the GPU. We’ll let you know if that changes.


Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started Techquila while in college to address my hardware passion. Although largely successful, it suffered from many internal weaknesses. Left and now working on Hardware Times, a site purely dedicated to. Processor architectures and in-depth benchmarks. That's what we do here at Hardware Times!

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