LPDDR4 is the mobile equivalent of DDR4 memory. Compared to DDR4, it has a reduced power consumption but does so at the cost of bandwidth. LPDDR4 has dual 16-bit channels resulting in a 32-bit total bus per DIMM. In comparison, DDR4 has 64-bit channels per DIMM. However, at the same time, LPDDR4 has a wider prefetch of 16n for a total of (16 words x 16 bit) 256 bits/32 bytes per channel and twice that for both channels combined.
DDR4, on the other hand, has two 8n prefetch banks per channel transferring data to and from the controllers at a time. The two paths are separate and can execute two independent 8n prefetches. This is done by using a multiplexer to time division multiplex its internal banks. This results in a total of 8 words x 64 bit= 512 bits (64 bytes) per cycle for each group.
LPDDR4 also has a more flexible burst length ranging from 16 to 32 (256 or 512 bits, 32 or 64 bytes), although 16 BL is mostly always used. DDR4, on the other hand, is limited to a burst length of 8 per cycle (128 bits or 16 bytes), although each bank can perform additional transfers.
To understand what burst-length means, you need to know how memory is accessed. When the CPU or cache requests new data, the address is sent to the memory module and the needed row, then the column is located (if not present, a new row is loaded). Keep in mind that there’s a delay after every step.
After that, the entire column is sent across the memory bus in bursts. For DDR4, each burst was 8 (or 16B). With DDR5, it has been increased to as much as 32 (up to 64B). There are two bursts per clock and they happen at the effective data rate. Furthermore, similar to LPDDR4, DDR5 has two 32-bit channels per DIMM for a total of four channels in a dual-DIMM configuration. The prefetch and BL have also been increased to 16. This figure is ideal as each cache line in memory is of the same size.
This design makes LPDDR4 much more power-efficient compared to standard DDR4 memory, making it ideal for use in smartphones with battery standby times of up to 8-10 hours. Micron’s LPDDR4 RAM tops out the standard with a 2133 MHz clock for a transfer rate of 4266 MT/s while Samsung follows shortly after with a clock of 1600MHz and a transfer rate of 3200 MT/s. In addition, as you can see in the tables below (from Wikipedia), LPDDR4 (1.1v) has a much lower voltage than DDR4 (1.3v) despite featuring similar or higher I/O bus clocks.
Finally, there’s the matter of the memory banks. Once again, LPDDR4 is optimized for low power over performance while the opposite is true for DDR4 memory. While DDR4 memory is made up of bank groups of 16 with each packing four individual memory banks, LPDDR4 and LPDD4X DIMMs have a total of eight memory banks per channel, resulting in an overall count of sixteen (16-bit x 2). LPDDR5 adopts a structure similar to DDR4, but that’s a discussion for another time.
LPDDR4 vs LPDDR4X: What’s the Difference?
Similar to how DDR5 reduces the voltage and power draw, LPDDR4X does the same. It cuts down the I/O voltage by 50% (1.12 to 0.61v), greatly reducing the power draw for both the memory as well as the memory controllers.
In addition, LPDDR4X increases the bandwidth from 3200MT/s to 4266MT/s (without OC). This is the result of a faster I/O bus clock (1600MHz to 2134MHz) and a memory array (200-266.7MHz). The command and address bus have been retained with 6 bits of SDR space. Finally, it takes lesser space on-chip and a single package can consist of up to 12GB of DRAM. On the downside, LPDDR4X isn’t backward compatible with LPDDR4. Even if a device is compatible with faster LPDDR4 memory, it may not work with LPDDR4X.
LPDDR4/LPDDR4x vs LPDDR5 vs DDR5
LPDDR5 is even more power-efficient than LPDDR4 and LPDDR4x. Thanks to the use of Dynamic Voltage Scaling (DVS), it adjusts the voltage and in turn the memory frequency as per load. Like LPDDR4/4x, LPDDR5 also features dual-16-bit channels, as well as a burst length of up to 32 (mostly 16).
DDR5, on the other hand, features two 32-bit channels per DIMM (DDR4 has one 64-bit per channel), with a burst length and prefetch of 16n per channel (DDR4 had half as much). Both DDR5 and LPDDR5 will support speeds up to 6400 Mbps as per the JEDEC standard, although we won’t see them with the first wave of modules. LPDDR5 also increases the density up to 32Gb per channel with operating voltages as low as 1.05/0.9V for VDD and 0.5/0.35V for I/O.
|LPDDR5 DRAMs||LPDDR4 DRAMs|
|Device size||2Gb to 32Gb (per channel) 4, 8, and 16 bank devices 1k, 2k, and 4k page sizes||2Gb to 16Gb (per channel) 8 bank devices 2k page sizes|
|Speed||Up to 6400 Mbps||Up to 4266 Mbps|
|Voltage||1.8V DRAM array 1.05V / 0.9V core 0.5V / 0.3 V I/O||1.8V DRAM array 1.1V core 1.1V / 0.6V I/O|
Thanks to the use of Dynamic Voltage Scaling (DVS), LPDDR5 can support two voltage modes: 1.05V (C) and 0.5V (I/O), while operating at higher frequencies and 0.9V (C) and 0.3V (I/O) while operating at lower frequencies.
LPDDR5 features include a new scalable clocking architecture for command/address (C/A) clock (CK) to allow easier SoC timing closure, and most of the features of DDR5 such as decision feedback equalizer (DFE), Write X feature to save power, and link ECC to enhance memory channel RAS.
Lastly, LPDDR5 also has a more flexible bank structure. While DDR5 packs 32 banks, its mobile variant can vary from 4 to 16 banks, with up to four bank groups (although 1-2 is the norm). Overall, LPDDR5 improves the power efficiency, along with the frequency and bandwidth of mobile memory, all the while retaining the flexibility that LPDDR4/LPDDR4x is known for.
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