After working on the fundamentals of the Zen CPU architecture at AMD, Jim Keller was recruited by Intel where he led a team of up to 10,000 people across multiple teams. According to Keller, the company had 60-70 different chips (SoCs) in development at a time, showing the incredible design and production capabilities of the chip giant. However, one particular area where the company initially struggled was the SoC IP. This is one of the key design aspects when you work on a chiplet/tile-based design, or any non-monolithic chip for that matter.
Keller states that Intel’s SoC IP wasn’t going too well when he first joined. The team had apparently just taken the existing monolithic chips, both server, and client and broken them into different pieces. Since these chips were designed for monolithic products, they wouldn’t work well in a chiplet-based SoC topology without significant compromises.
I’m guessing Keller is referring to the early development of Lakefield which uses the 3D packaging technology, Foveros. The SoC turned out to be a very average product with some of the key issues being poor core-to-core latencies and bandwidth, poor cache hierarchy, and higher than marketed real-world power draw.
A couple of years before I joined, they started what’s called the SoC IP view of building chips, versus Intel’s historic monolithic view. That to be honest wasn’t going well, because they took the monolithic chips, they took the great client and server parts, and simply broke it into pieces. You can’t just break it into pieces – you have to actually rebuild those pieces and some of the methodology goes with it.
We found a bunch of people [internally] who were really excited about working on that, and I also spent a lot of time on IP quality, IP density, libraries, characterization, process technology. You name it, I was on it. My days were kind of wild – some days I’d have 14 different meanings in one day. It was just click, click, click, click, so many things going on.Jim Keller (Source)