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Intel’s Willow Cove Core (Tiger Lake) is Basically Sunny Cove w/ More Cache: Identical Decode, EUs, and BP

One of the main highlights of Intel’s Architecture Day 2020 was the next-gen Willow Cove core that will power the 11th Gen Tiger Lake CPUs. However, it turns out that there’s not much “next-gen” about it. Essentially, you’re looking at the Sunny Cove core stuffed with significantly more cache and fabbed on a more refined version of the 10nm node.

Not to say that it’s just like the Skylake-refresh-refresh strategy that Intel adopted over the last half-decade, but it sure reminds me of it. However, unlike the former, you can expect some healthy IPC boosts with Sunny Cove and Tiger Lake. In essence, most of these advances come from improvements to the process node and memory system, rather than the compute part of the core. Let’s have a look.

The third iteration of the 10nm node which Intel is now calling SuperFin instead of FinFET is the first core upgrade. One of the primary drawbacks with the 10th Gen Ice Lake CPUs powered by Sunny Cove was the frequency-voltage scaling: It was less than ideal, especially after coming from the super-mature 14nm Whiskey Lake chips.

The new SuperFin transistors aim to fix this very issue, allowing significantly higher clock speeds, something that we’ve already seen in the past. As an example, while Ice lake was limited to 4GHz, Willow Cove may as well exceed 5GHz in certain scenarios. This will, however, come at a cost. Where the former had a default TDP of 15W, Tiger Lake will come with a stock power rating of 25-28W.

Interestingly, this means that the load (PL2) power draw value for Tiger Lake-U may as well touch the 65W mark when running AVX-512 instructions. Ice Lake hit 50W when running the same, and considering that Tiger has a 10W+ higher base clock, the chances of it hitting the 65W mark is very likely.

2.5x L2 Cache, 50% More L3 Cache

Technically, the only change to the core architecture with Willow Cove is with respect to the L2 and L3 cache hierarchy. The L2 cache gets a massive increase of 2.5x which should significantly improve hit-rates (by around 50%+), but at the same time, it’ll increase the latency as larger cache sizes take longer to access.

Sunny CoveWillow Cove
512 KB
8-way
Inclusive
13-cycles
1.25 MB
20-way
Exclusive
25-cycles?

Another advantage with the L2 cache in Willow Cove is that it’s non-inclusive, unlike Sunny Cove which was inclusive. The former is generally faster for the following reasons:

Non-inclusive or exclusive cache makes the L2 cache act like a victim cache. As such, when a block is evicted from L1 it usually is sent to L2.

With inclusive cache, there’s a need for back invalidation from the L2 to L1 cache whenever a block is evicted from the former. Basically, with a non-inclusive cache, every block present in the L1 cache is also present in the L2 cache. With exclusive caches, that’s not true, and it can violate cache coherency in certain cases. To avoid this, certain workarounds need to be implemented in the caching hardware. The shared L3 cache has also been increased by a lofty 50% from 8MB 16-way to 12MB 12-way. However, at the same time, the decrease in associativity means that we won’t see an improvement by the same figure.

LPDDR5 Memory and Better Security

In Tiger Lake, the Willow Cove cores will be paired with the faster LPDD4x-4266 and in some cases even LPDDR5-5400 memory for a bandwidth of as much as 86.4GB/s. Although, the latter won’t be seen this year, it should start shipping with premium Athena-class notebooks next year.

As for security, Intel is making it a central theme with Tiger Lake for obvious reasons. The 11th Gen Tiger Lake CPUs will support Control-Flow Enforcement Technology (CET) that helps protect against return/jump oriented attacks. Indirect Branch Tracking is also included but will require some software-level support.

Finally, Tiger Lake also follows AMD’s Renoir APUs by including support for Total Memory Encryption. It keeps user data contained in the main memory safe from hardware attacks. It has a very minimal performance impact of 1-2% in most scenarios.

Areej

Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started Techquila while in college to address my hardware passion. Although largely successful, it suffered from many internal weaknesses. Left and now working on Hardware Times, a site purely dedicated to. Processor architectures and in-depth benchmarks. That's what we do here at Hardware Times!
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