With Alder Lake, Intel is redefining the basic principles of its consumer processors. Taking a leaf from the Arm rulebook, the chipmaker has integrated its Atom cores (efficiency) cores into its high-performance desktop and mobile designs, intending to boost multi-threaded capabilities, all the while improving power efficiency. It’s important to note that, unlike mobile Arm processors, the delta between the Golden Cove and Gracemont cores isn’t that wide, and at the end of the day, it boils down to the former being a wide x86 high-frequency design, with the latter being wider still, but optimized for lower frequencies.
Update: The above slide from Videocardz mentions the M5 segments for tablets with 1 performance and four efficiency cores, and a TDP of 5-7W. Intel’s Arc Day slides have no mention of this stack, but it may be announced later on.
Till now, the low-end/low-power Atom processors have featured…well, the Atom cores. However, with Alder Lake, that is going to change. The ultra-mobile lineup (consisting of the Celeron N4000/N5000/N6000 series) which is presently represented by Jasper Lake, will also be replaced by a hybrid SKU stack.
While Jasper Lake topped out at just four cores, Alder Lake Ultra Mobile (BGA) processors will feature up to 10 cores, with eight efficiency (Gracemont) cores and two (Golden Cove) performance cores. On the other hand, the standard mobile processors (U and Y), will feature up to four high-performance cores and eight efficiency cores. It looks like the eight efficiency cores are common to all Alder Lake designs from the 125W LGA 1700 to the 5W BGA socket.
Going by Intel’s Architecture Day 2021 slides, it looks like the desktop and high-performance mobile processors will be DDR5-4800/DDR4-3200 memory, while the low-power mobile designs will leverage LPDDR5-5200 and LPDDR4x-4266:
Meanwhile, x16 PCIe 5.0 lanes, along with x4 PCIe 4.0 are also another noteworthy addition to I/O, although, I’m not sure whether it’ll be common to the low-power designs as well. It’s very likely that the lower-end designs will be limited to PCIe Gen 4 or x8 PCIe Gen 5 lanes.