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Intel was Originally Planning a 60-Core Xeon Sapphire Rapids-SP CPU w/ 16-Core Chiplets/Tiles [Rumor]

It appears that Intel was originally planning 60-core 4th Gen Xeon Sapphire Rapids-SP in order to compete with AMD’s Epyc Milan and Genoa lineups, but unsatisfactory yields forced the chipmaker to reduce the core count to 56. This info was shared by @YuuKi_Ans on Twitter. According to the well-reputed source on Intel processors, the company was supposedly working on 16-core tiles (chiplets) with one core disabled, resulting in a four-tile part packing a total of 60-cores.

Now, due to lower-than-expected 10nm ESF (7) yields, Intel has been forced to rely on 15-core tiles (one core disabled each die), leading to a maximum of 56-cores with four-tiled parts. This is a bit strange as I don’t see how a single core would have made much of a difference in terms of yields. The company could have simply disabled two cores instead of one on each die and called it a day. It’s possible that the original plan was to enable all 15-cores on the tiles, resulting in a total core count of 60 for the top-end Sapphire Rapids SKU. Cutting out a core from the tile design seems like a much less efficient approach than simply disabling it in the final implementation.

Areej

Computer hardware enthusiast, PC gamer, and almost an engineer. Former co-founder of Techquila (2017-2019), a fairly successful tech outlet. Been working on Hardware Times since 2019, an outlet dedicated to computer hardware and its applications.

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