The 2nd-Generation Intel Xeon Scalable platform provides the foundation for a powerful data center platform that creates a leap in agility and scalability. Intel Corporation on April 2, 2019, introduced a portfolio of data-centric tools to help its customers extract more value from their data. (Credit: Intel Corporation)
It appears that Intel was originally planning 60-core 4th Gen Xeon Sapphire Rapids-SP in order to compete with AMD’s Epyc Milan and Genoa lineups, but unsatisfactory yields forced the chipmaker to reduce the core count to 56. This info was shared by @YuuKi_Ans on Twitter. According to the well-reputed source on Intel processors, the company was supposedly working on 16-core tiles (chiplets) with one core disabled, resulting in a four-tile part packing a total of 60-cores.
It seems that it is still a problem of yield … Before they told me that it was 4×16 but each one was missing, but now it is 4×15 and each one is missing …
Now, due to lower-than-expected 10nm ESF (7) yields, Intel has been forced to rely on 15-core tiles (one core disabled each die), leading to a maximum of 56-cores with four-tiled parts. This is a bit strange as I don’t see how a single core would have made much of a difference in terms of yields. The company could have simply disabled two cores instead of one on each die and called it a day. It’s possible that the original plan was to enable all 15-cores on the tiles, resulting in a total core count of 60 for the top-end Sapphire Rapids SKU. Cutting out a core from the tile design seems like a much less efficient approach than simply disabling it in the final implementation.
Processors, PC gaming, and the past. I have written about computer hardware for over seven years with over 5000 published articles. I started during engineering college and haven't stopped since. On the side, I play RPGs like Baldur's Gate, Dragon Age, Mass Effect, Divinity, and Fallout. Contact: areejs12@hardwaretimes.com.
