In a newly released video, Intel CEO, Bob Swan has shared that the company is gearing up to launch its Cooper Lake-SP for the HPC and AI markets. Originally expected to launch at Computex which has now been shelved due to the global pandemic, Team Blue is going to be doing an online reveal like most of its peers.
As you might have heard the mainstream version of Cooper Lake, Whitley has been canceled, and we’ll only be seeing the multi-socket 2S and 4S Cedar Island platform which will feature up to 56 cores per socket, thanks to an MCM design. That’s right: two to tree Xeons glued together. As HPC and AI are the highlights of Cooper Lake, it’ll introduce multiple new instructions relevant to the sector such as BFLOAT16 and AVX512 BF16. The former is a single-precision (FP32) format with a reduced mantissa, limiting the precision to half, ideal for accelerating AI workloads. This s similar to NVIDIA’s TF32 introduced with the A100.
The other main features of Cooper Lake include an increased bandwidth (174.84 GiB/s, up from 119.209 GiB/s), support for octa-channel memory (up from hex) and the use of Optane DC DIMMs based on Barlow Pass.
Cooper Lake is expected to be succeeded by the 10nm Ice Lake-SP which will be the first core upgrade in nearly five years. It’ll features the Sunny Cove architecture and come with massive IPC improvements. However, Ice Lake-SP is going to be limited to under 30 cores, unlike Cooper Lake, and won’t get an MCM chip, either.
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In the video, Swan also reminded everyone that Tiger Lake is on track for a late summer launch, with an aim to retake the mobile processor crown. Considering that it’ll be limited to quad-core designs and the sub-30W low-power notebook space, it’ll mostly be a marketing stunt with limited supply. The Gen12 Xe graphics featured on the chips will be the important bit. They are expected to represent the fastest iGPUs on the market, beating AMD’s 7nm Vega iGPUs found on Renoir.
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