Intel’s Ponte Vecchio HPC GPU is one of the most advanced chips ever designed. With an overall transistor count exceeding 100 billion, and total silicon of 3,100 mm^2, the HPC accelerator will combine three different nodes from Intel’s internal foundry and TSMC’s advanced nodes. The compute tiles will be fabbed on TSMC’s N5 (5nm) node, Xe-Link tiles on TSMC’s N7 (7nm) node, and the Foveros/Rambo Cache tiles on the Intel 7 (previously 10nm ESF) node.
| Chiplet/Tile | Number | Process Node |
|---|---|---|
| Compute Tile | 16 | TSMC N5 |
| RAMBO Cache Tiles | 8 | Intel 7 |
| Foveros Base Tiles | 2 | Intel 7 |
| Xe-Link Tiles | 2 | TSMC N7 |
| HBM2e Tiles | 8 | |
| EMIB Tiles | 11 | |
| Total Active Tiles | 47 | |
| Thermal Tiles | 16 | |
| Total Tiles | 63 |
Overall, Ponte Vecchio will consist of 63 tiles. Out of these 16 will be thermal/structural tiles, with the rest being Compute, Xe-Link, HBM2e, EMIB, Foveros, and Rambo Cache tiles. The RAMBO and Foveros tiles will be fabbed on the Intel 7 node while the Compute tiles and Xe-Link tiles will leverage TSMC’s N5, and N7 nodes, respectively.
Ponte Vecchio combines Intel’s leading-edge packaging technologies, namely Foveros and EMIB. The former is a 3D stacking technique, and the latter is a die-to-die 2D interconnect:
The Base Foveros dies are connected by Co-EMIB interconnects, as well as to the HBM dies. EMIB is also used to connect the compute and RAMBO tiles, in addition to the Xe Link and HBM dies.
Unsurprisingly, Ponte Vecchio with a thermal design target of 450W has a Tc limit of 76 degrees on the compute/RAMBO dies. The 600W design has a Tc limit of 81 degrees for the computer die, and 78 degrees for the Xe-Link die. Overall, Intel’s packaging floorplan looks a lot like AMD’s…on steroids.
