Intel today launched its Cascade Lake-SP, forming the Cedar Island platform and the first wave of 3rd Gen Xeon Scalable processors. These chips will be for 4S to 8S scalable socket configurations, while Ice Lake-SP slated to launch in H2 2020 will be for 1 and 2 socket server platforms, and form the Whitley Platform.
There are three main upgrades that come with Cooper Lake: BFloat16 for AI workloads, wider CPU to CPU bandwidth (likely a response to AMD’s Epyc) and updated memory and Optane support.
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BFloat16 is essentially a new data unit that utilizes the BF16 format to offer the precision of FP32 at the speed of FP16. This is very much like NVIDIA’s TF32 compute introduced with the A100 which is supposed to be 20x faster than FP32 while producing a standard IEEE FP32 output:
Intel has also doubled the socket-to-socket bandwidth with Cooper Lake. Till now, the Xeon scalable chips have had three UPI (Ultra Path Interconnect) between the various CPUs in a system. With Cooper Lake, that has been increased to six. On the downside, each CPU can only connect to three others
Each CPU in a Cooper Lake-SP will be connector to its peers using two UPI links, with each running at 10.4 GT/s, for a total of 20.8 GT/s, essentially doubling the bandwidth compared to Cascade Lake.
The last major upgrade that Cooper Lake has received is with respect to memory. Cooper Lake supports up to DDR4-3200 with the higher-end Platinum CPUs. This increases the overall bandwidth from 23.46GB/s per channel to 25.60GB/s.
As far as max memory is concerned, the entry-level Xeon chips will support up to 1.125TiB memory, up from 1TiB. This means you can connect six 64GB DIMMs and six 128GB modules. However, at the same time, a full 12* 128GB config is still not supported.
There will be higher memory capacity CPUs designated as the “HL” line with support for up to 4.5TB of memory. Intel’s second-gen (Barlow Pass) Optane DC Persistent memory will also be supported with Cooper Lake-SP. The platform supports modules ranging from 128GB to 512GB, all running at the same speed as the main memory (2666MHz).
Cooper Lake-SP offers 48 PCIe 3.0 lanes, still a far cry from AMD Rome’s 64 PCIe 4.0. Although it’s a step up from Cascade Lake, it’s still not quite up there. Explains why NVIDIA ditched the Xeons for Epyc in the DGX A100. The prices aren’t representative of the features you get either. The Rome parts are roughly half as expensive, all the while offering twice as much performance.
|EPYC 7742||64 / 128||2.25||3.40||256 MB||225 W||$6950|
|EPYC 7702||64 / 128||2.00||3.35||256 MB||200 W||$6450|
|EPYC 7642||48 / 96||2.30||3.20||256 MB||225 W||$4775|
|EPYC 7552||48 / 96||2.20||3.30||192 MB||200 W||$4025|
|EPYC 7542||32 / 64||2.90||3.40||128 MB||225 W||$3400|
|EPYC 7502||32 / 64||2.50||3.35||128 MB||200 W||$2600|
|EPYC 7452||32 / 64||2.35||3.35||128 MB||155 W||$2025|
|EPYC 7402||24 / 48||2.80||3.35||128 MB||155 W||$1783|
|EPYC 7352||24 / 48||2.30||3.20||128 MB||180 W||$1350|
|EPYC 7302||16 / 32||3.00||3.30||128 MB||155 W||$978|
|EPYC 7282||16 / 32||2.80||3.20||64 MB||120 W||$650|
|EPYC 7272||12 / 24||2.90||3.20||64 MB||155 W||$625|
|EPYC 7262||8 / 16||3.20||3.40||128 MB||120 W||$575|
|EPYC 7252||8 / 16||3.10||3.20||64 MB||120 W||$475|
As already reported earlier, Ice Lake-SP (Whitley) will land sometime in H2 2020 and Sapphire Rapids based on the Willow Cove core and the third iteration of Intel’s 10nm process is also on track for a late 2021 launch.