At HotChips today, Intel detailed its Ice Lake-SP server architecture slated to launch later this year. Although the same 10nm+ Sunny Cove core powers both the client and server lineup, there are some significant differences between the two implementations. The Sunny Cove core on the Xeon processors is actually closer to the Willow Cove architecture powering Tiger Lake. Before we dig in, let’s recall how Sunny Cove and Willow Cove are nearly identical in terms of the core design:
- Intel’s Willow Cove Core (Tiger Lake) is Basically Sunny Cove w/ More Cache: Identical Decode, EUs, and BP
There are basically three main differences between Sunny and Willow Cove: The latter features a more mature 10nm node, larger L2 and L3 cache, and faster memory support. Out of these, the change in cache configuration is the primary modification to the core architecture while the other two are improvements to the process node and memory controller.
Well, guess what? The Sunny Cove in Ice Lake-SP features an identical L2 cache configuration to Willow Cove:
Both Willow Cove and the server Sunny Cove feature 1.25MB of L2 cache and a 384 OoO execution window while the client SNC has 512KB of L2 and a 352 window OoO execution. Furthermore, there’s a 512-bit FMA in the server core (AVX-512) while the client core has the same unit with 256-bit width. The former should technically be able to execute two AVX-512 instructions (one using the FMA 512 and another by combining the two 256-bit FMA units). Sunny Cove client, on the other hand, can do one 512-bit FMA (fused multiply and add) or two 256-bit FMA per cycle. And despite this, both the server and client cores promise an average IPC gain of 18%, sounds unlikely.
This makes the Sunny Cove to Willow Cove transition a lot more confusing and makes me wonder if the SuperFin stuff is actually legit or just more marketing mumbo-jumbo. Because other than that, the differences between the two cores seem rather minimal. (Phentermine 37.5)