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Intel Expected to Increase Xeon-SP Core Count to 64 (Finally) w/ Emerald Rapids in 2023

Intel might finally catch up to AMD in terms of core counts in the server space with Emerald Rapids. That is if it launched this year and not two years from now. Sapphire Rapids-SP is slated to push the maximum core count to 56 (from 40 in Ice Lake-SP) next year. Its successor, Emerald Rapids-SP (according to Moore’s Law is Dead) will further push the compute density to 64 cores, bringing it on par with AMD’s present offerings.

Unfortunately for Intel, AMD won’t be sitting idle and has already increased the core count of its next-gen Epyc Genoa processors to 96, with 128 PCIe lanes, DDR5 memory possibly twice as much L3 cache as Milan (256MB), thanks to the use of 3D V-Cache.

Emerald Rapids-SP or the 5th Gen Xeon Scalable processors will feature the Raptor Lake cores, fabbed on Intel’s 7 node (10nm ESF). The transition from Golden to Raptor Lake can be thought of as that between Sunny to Willow Cove, except it’ll actually improve the IPC a bit. The core count is expected to increase from 56 on Sapphire to 64 on Emerald Rapids, plus improved I/O and higher boost clocks.

Since it’s essentially a refresh, Emerald Rappuds will retain the Eagle Stream platform and the accompanying LGA 4677 socket. The PCIe 5.0 lane count will increase to 80, and memory speeds to 5600 MT/s.

Finally, Granite Rapids-SP will launch between 2023-24 with a new process node and core architecture. We’re looking at the Intel 4 node (originally 7nm) and the Redwood Cove core architecture. It will refine the tiled design with several compute dies and an overall core count of 120. Similar to Sapphire and Emerald, Granite Rapids will also feature on-die HBM memory on select SKUs, as well as Rambo Cache to act as bridges along the EMIB interconnect.

Emerald Rapids should clash with AMD’s Bergamo (or its successor), also expected to feature 128 cores and 256 threads on TSMC’s 5nm, with a slightly earlier launch window.

Source: https://youtu.be/g44zQII9GV4

Areej

Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started my first technology blog, Techquila while in college to address my hardware passion. Although largely successful, it was a classic example of too many people trying out multiple different things but getting nothing done. Left in late 2019 and been working on Hardware Times ever since.

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