In a blogpost on Medium, Intel has inadvertently confirmed the existence of 8 core Tiger Lake-H CPUs. While talking about the new non-inclusive L3 cache, Boyd Phelps, VP of the CCG group explained that each core in Tiger Lake had access to 12MB of LLC for quad-core chips and up to 24MB for 8 core dies.
We also added a 3MB non-inclusive last-level-cache (LLC) per core slice. A single core workload has access to 12MB of LLC in the 4-core die or up to 24MB in the 8-core die configuration (more detail on 8-core products at a later date).Medium
This isn’t the first time we’ve heard of octal-core Tiger Lake parts leveraging Intel’s 10nm++ node, but it’s the first time it has been officially mentioned by an Intel executive. Intel is expected to launch the 10nm Tiger Lake-H lineup for high-performance 45W notebooks in the first quarter of 2021, although memory support will be limited to DDR4. Tiger Lake-U, on the other hand, will use LPDDR5. You can read our in-depth explanation of the Willow Cove core and Gen12 Xe graphics powering the below:
- Intel’s Willow Cove Core (Tiger Lake) is Basically Sunny Cove w/ More Cache: Identical Decode, EUs, and BP
- Intel Gen12 Xe Graphics Architectural Deep Dive: The Bigger, the Better
The second interesting bit of information that has come forward is with respect to the DG1 discrete graphics which is basically the Gen12 Xe iGPU in dGPU form with dedicated memory and higher clocks. In an interview with PC Watch, Chris Walker, VP of Intel’s Mobile Client Division explained that Intel will be making its DG1 discrete graphics solution to OEMs for use in laptops in the future. When asked whether the newly released Tiger Lake notebooks will feature it, Walker replied by saying none of the announced notebooks have the DG1 dGPU, but it’ll be available on future platforms.
Intel already promises 1080p gaming with its 15-28W Tiger Lake-U CPUs (a first for ultra-thin 12-14 inchers). DG1 is going to be around 20-25% faster than the Gen12 Xe iGPUs with its own discrete graphics memory, higher clock speeds, and a separate cooling solution. In terms of architecture and feature-level, the two should be identical. One of the primary differences will be with respect to the low-level cache and the memory controller.
While the Gen12 iGPU features 3.8MB of L3 cache, the DG1 will pack a massive 16MB of it. Furthermore, it’ll have its own dedicated 128-bit wide memory controller, replacing the two ringbuses on Tiger Lake-U. The boost clock for the DG1 should also be higher than 1.6GHz, maybe even around 1.8GHz, thanks to the SuperFin technology. The downside with DG1 is that it lacks DirectX 12_2 feature level support which is already supported by all of NVIDIA’s Turing and AMD’s upcoming RDNA 2 GPUs.