Intel launched its 12th Gen Alder Lake-S processors last year, bringing a hybrid core architecture to the x86 market for the first time. Featuring eight Golden Cove cores and eight Gracemont cores, these cutting-edge microprocessors excel not only in the single-thread workloads, but heavily multi-threaded applications as well. However, one oddity with the Alder Lake chips is the lack of (official) AVX-512 support. Intel has stated multiple times that the advanced 512-bit instructions won’t be available on the 12th Gen consumer offerings. However, board partners have time and again found ways to enable it.
This time Intel has put its foot down by completing fusing off AVX-512 on future shipments of Alder Lake-S processors. This means no microcode or firmware tweaks will be able to re-enable it on newly shipped units. This story was first published by TomsHardware who followed up with Intel and got the following statement from the company :
Although AVX-512 was not fuse-disabled on certain early Alder Lake desktop products, Intel plans to fuse off AVX-512 on Alder Lake products going forward.” -Intel Spokesperson to Tom’s Hardware.
Intel Spokesperson to Tom’s Hardware.
AVX-512 is largely irrelevant to mainstream consumers and gamers. It’s primarily of importance to the data center, and to an extent, content creators, who can benefit from accelerated scientific simulations, financial analytics, machine learning, inferencing, 3D modeling, image/video processing, cryptography, and data compression.
Intel will be promoting AVX-512 on its Xeon processors, with the workstation range getting it as an add-on feature. As reported earlier, Intel will be gating AVX-512 and AMX instructions behind a paywall of sorts, much like paid DLCs in video games. The feature known as Software Defined Silicon “SDSi” will be enabled primarily on server and data center nodes via the Linux kernel, allowing vendors to offer special “accelerators” or “add-ons” to clients for a price.
