Intel Believes its Tiles are a Better Approach to the MCM Design than AMD’s Chiplets

Although both Intel and AMD are now officially invested in an MCM approach while designing their processors, the two longtime rivals are using different terms to define these fairly similar paths. AMD’s terminology is quite well known at this point: Chiplets, CCXs, and CCDs, these are all the same names for a single die on a base substrate. Team Red uses its Infinity Fabric interconnect to connect these chiplets which has evolved significantly since it was conceived nearly half a decade back. It’s used in the Ryzen CPUs, APUs, RDNA 2 GPUs as well as some of the company’s semi-custom designs. The latest iteration will also be used to power the Frontier Supercomputer wherein the IF 3.0 interconnect will be used to connect four MI200 GPUs with an Epyc Trento CPU in a mesh network, offering unparalleled scalability and bandwidth with unified memory, all the while maintaining simpler programmability.

Intel, on the other hand, is calling its individual dies: tiles (although some key execs like Raja Koduri still call them chiplets from time to time). At this point, it’s still somewhat unclear whether the company plans to use the EMIB interconnect for connecting all its “tiles” or if there’s some new interconnect in the works. The reason being that EMIB is primarily used for connecting a central die to chiplets or memory off-die (KBL-G is an exception). Either way, at this point, we only know of EMIB and Foveros with the latter being utilized for 3D stacking.

With EMIB, Intel equips the substrate with multiple, small embedded silicon connections, allowing the substrate to host the primary die with small-distance (EMIB) interconnects with multiple compute or I/O chiplets. The Agilex FPGA is one of the primary implementations of such a design, with the Kaby Lake-G processor also utilizing it to connect the GPU with the HBM memory.

Foveros is used for 3D stacking which can be used to connect different chips by TSVs (through silicon vias, a via being a vertical chip-to-chip connection). This is basically how the Lakefield SKU was designed, allowing Intel to connect the compute, I/O, graphics, and DRAM dies while keeping them all on the same substrate. Here, the I/O die at the bottom of the stack acts as an “active interposer” and routs the data between the top dies.

As per Gelsinger, Intel’s newly appointed CEO, the company’s 3D packaging technology is “perfect”, giving it the ability to go with “tiles” rather than “chiplets”. Intel believes that its 3D stacked “tiled” approach is better than the 2D chiplet strategy used by AMD as it allows for denser chips. At the same time, it’s important to note that AMD has been using the MCM design for over four years now and by the time Intel actually releases a 3D stacked processor, the former will likely have already announced its own. TSMC’s 3D stacking technology called SoIC is presently being tested with AMD being one of the early adopters.

One of the cool things that I found when I came back was that, even though there were some issues in the process technology, the 3D packaging technology is perfect. Unquestioned leadership. And this gives us the ability to not be doing chiplets, but to be doing tiles. Because of that packaging technology, we don’t have to buffer interconnect, it’s actually like a long wire on-chip.¬†And that packaging technology is part of what gives us a really cool advantage in the next-generation of our process roadmap where we’re going to be able to mix and match tiles from different process technologies but bring them together as if they’re one single chip. We’ll be moving from system-on-chip to system-on-package.


If I’m being completely honest, I’d say that Intel is quite a bit behind AMD when it comes to the interconnect. With Lakefield, despite using a ring topology and the latest packaging tech including Foveros and EMIB, the inter-core latency is pretty horrendous. And this is just a 4+1 core design we’re talking about here. With more complicated designs featuring up to 16 cores, it could be much worse. Compared to this, AMD’s inter-core latencies are half as much with Zen 3.

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