Intel’s Linux driver team has started work on its chiplet-based GPUs. Initial support for multi-tile GPUs was patched in last Friday following the groundwork for the Xe-HP architecture. The chipmaker plans to launch its first chiplet GPU with Ponte Vecchio sometime in the next few years. Ponte Vecchio will feature up to 47 tiles (chiplets/dies) resulting in a mega-chip that boasts over 100 billion transistors. The dies will be fabbed across different foundries including TSMC and Intel’s in-house fabs.
Some of our upcoming platforms, including the Xe_HP SDV, support a “multi-tile” design. A multi-tile platform is effectively a platform with multiple GT instances and local memory regions, all behind a single PCI device. From an i915 perspective, this translates to multiple intel_gt structures per drm_i915_private. This series provides the initial refactoring to support multiple independent GTs per card, but further work (especially related to local memory) will be required to fully enable a multi-tile platform.Intel Graphics Driver Patch on Linux (Via: Phoronix)
Note that the presence of multiple GTs is largely transparent to userspace. A multi-tile platform will advertise a larger list of engines to userspace, but the concept of “tile” is not something userspace has to worry about directly. There will be some uapi implications later due to the devices having multiple local memory regions, but that aspect of multi-tile is not covered by this patch series and will show up in future work.
The patch notes mention that developers won’t have to worry about writing separate code for multi-tile GPUs. The API and the driver will take care of that, making the GPU appear as a single tile/entity, thereby simplifying the programming part of things. We expect a similar level of abstraction from AMD’s upcoming Navi 31 and NVIDIA’s Hopper MCM graphics cards. These designs will also feature at least two separate dies on the same substrate, bringing about the next stage in gaming and high-performance computing.