During its HotChips presentation today, Intel detailed its plans for its upcoming client architectures namely Meteor Lake, Arrow Lake, and Lunar Lake. Like Lakefield, these next-gen lineups will leverage 3D packaging technology “Foveros” alongside a disaggregated or tiled/chiplet design. Unlike the first implementation of Foveros, Meteor Lake will feature a dummy base tile (interposer) without any logic. The four functional chiplets or tiles will be 3D stacked atop this skeleton die.
The base die or interposer will be fabbed on Intel’s legacy 22FFL (or Intel 16) node while the CPU compute tile will leverage the Intel 4 node (formerly 7nm). Unfortunately for Team Blue, this is the only advanced tile on Meteor Lake to originate from Intel’s own foundry. The remaining three will all come from TSMC’s fabs. (kennedyandperkins)
| CPU Tile | Intel 4 |
| 3D Foveros Base Die | 22FFL/Intel 16 |
| GPU Tile | TSMC 5nm (N5) |
| SoC Tile | TSMC 6nm (N6) |
| I/O Tile | TSMC 6nm (N6) |
The GPU tile, as rumored a while back, will be a product of the TSMC 5nm (N5) process while the SoC and I/O die will be based on the 6nm (N6) node. Initially, it was thought that the tGPU tile would be fabbed on the 3nm (N3) process but for whatever reason, that honor will now pass onto Arrow Lake.
Much like AMD’s Infinity Fabric interconnect which is now a crucial part of its chip designs (but proprietary), Intel is proposing an “Open Chiplet Ecosystem” through the Universal Chiplet Interconnect Express (UCIe). Furthermore, the way Meteor Lake and Arrow Lake have been mentioned together, it does seem like they’ll form a single generation or platform rather than two distinct ones.
