According to info shared by the reputed Twitter source, @momomo_us, Intel’s upcoming 3rd Gen Ice Lake-SP Xeon processors will feature as many as 40 Sunny Cove cores with a base clock of 2.3GHz. Other than the core count, the memory channels and PCIe lanes have also been beefed up. You’re now looking at 64 PCIe lanes (still less than Rome and Milan, but a step up from Cascade Lake) and 8-channel DDR4-3200 RAM with ECC. (Xanax)
The 3rd Gen Ice Lake Xeon family will be composed of two configurations, namely XCC (Extreme Core Count) with 16, 18, 28, 32, 36, 38, and 40 cores, and the HCC (High Core Count) which starts off with just 8 cores and tops out at 28 cores. The top-end part from the XCC lineup will feature up to 40 cores and a base clock of 2.3GHz, with a TDP of 270W. That’s just 10W less than the TDP of the 64 core AMD Epyc Rome chips. Intel is likely pushing the TDP up to achieve higher operating clocks than otherwise possible.
The above CPU is a 24 core part with a massive 57MB L3 cache buffer running in 2S config, resulting in a total core count of 48 for the entire system. While that’s a far cry from the 128MB of L3 cache found on 24C Epycs, it’s a monumental increase from the 35.75MB of L3 cache featured on the Cascade Lake-SP. In line with the mobile Ice Lake-U processors, the L1 and L2 cache on Ice Lake-SP has also been beefed up compared to the older Skylake core.
Compared to the consumer-grade implementation of Sunny Cove, the server parts are getting a larger L2 cache, plus a second FMA FP unit for enhanced AVX512 performance.
