Intel 10nm Ice Lake-SP CPUs Facing Clock Scaling Issues going from Idle to Load

Although Intel is presently working on the third iteration of its 10nm node with Tiger Lake, there are still several issues with the process. With the 10nm client Ice Lake processors, the boost clocks were notably lower than existing 14nm parts due to yield issues and the overall supply was also quite limited at the time of launch. Tiger Lake promises to tackle both these problems, but it appears that the Ice Lake-SP (server) will still struggle with some of them.


A recent Linux patch highlights a similar issue. However, this one isn’t with regard to the boost clock. Rather it pertains to the CPUs’ power state. The ICX (Ice lake server CPUs) seem to be facing a latency penalty while going from the low-power C state (idle) to load. While the expected latency is 41us, the processors are taking 3x as much: 128us.

Intel’s going the brute-force way with this patch by simply disabling the C6 state and implementing a separate C1E idle state. It’s unclear whether this will affect the load power consumption, but it’ll definitely reduce power efficiency.


Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started Techquila while in college to address my hardware passion. Although largely successful, it suffered from many internal weaknesses. Left and now working on Hardware Times, a site purely dedicated to.Processor architectures and in-depth benchmarks. That's what we do here at Hardware Times!

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