Future AMD Ryzen and Epyc CPUs May Feature a Level 4 Cache (L4)

AMD might introduce a fourth level cache (L4) with its 4th Gen Ryzen and Epyc Genoa CPUs to address the increasing core counts. Earlier, we had reported that the core counts with Zen 4 might double as the die size is said to increase despite a nearly 80% increase in density (5nm EUV). The patent shared by Underfox illustrates the addition of a large L4 cache in virtual environments:

Till now, AMD’s Ryzen and Epyc processors feature an L1 and L2 cache that is unique to each core. Then the L3 cache is shared between the cores on a CCX. As per reports, Zen 4 will unify the L3 cache to service the entire CCD (2x CCXs). This new patent includes the possibility of an L4 cache that will service the cache misses of the L3 cache featured on the CCDs, essentially servicing the entire CPU.

  • What is a CCX vs CCD in an AMD Ryzen Processor
  • AMD Navi vs Vega: Differences Between RDNA and GCN Architecture

AMD recently introduced a third-level cache with its Navi GPUs while NVIDIA’s Turing lineup still features two cache levels. However, here the L4 cache is primarily aimed at virtualized environments where multiple users share the same processor or set of processors. It’s unclear how having a common L4 cache for all the CCDs will improve performance, especially considering that they’ll be in use by different users. You can read more about cache memory here:

  • Difference Between L1, L2, and L3 Cache in a CPU: A Look at Cache-Memory Mapping

Areej Syed

Processors, PC gaming, and the past. I have been writing about computer hardware for over seven years with more than 5000 published articles. Started off during engineering college and haven't stopped since. Mass Effect, Dragon Age, Divinity, Torment, Baldur's Gate and so much more... Contact: areejs12@hardwaretimes.com.
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