Memory and StorageNews

DDR5 Memory with Transfer Speeds up to 8400Mbps and 64Gb Density Detailed

SK Hynix has detailed the specifications of the next-gen DDR5 memory standard, and they’re a substantial step above the existing DDR4 modules. DDR5 aims to reach bandwidths as high as 4800Mbps per DIMM, a hefty 50% gain over DDR4’s 3200Mbps. This massive uplift is achieved via the following advances in the memory structure:

32-Bank Structure: DDR5 uses a 32 bank structure with 8 bank groups, twice as much as DDR4’s 16 bank design. This effectively doubles the memory access availability. To complement this, DDR5 also adopts the Same Bank Refresh Function. Unlike DDR4, this allows the next-gen memory to access other memory banks while the rest are operating or refreshing.

Burst Length: With DDR4, the burst rate was limited to 8, allowing transfers of up to 16B from the cache at a time. DDR5 increases this to 16, with support for even 32-word mode, which allows up to 64B cache line fetch with just one DIMM.

To understand what burst-length means, you need to know how memory is accessed. When the CPU or cache requests new data, the address is sent to the memory module and the needed row, then the column is located (if not present, a new row is loaded). Keep in mind that there’s a delay after every step.

After that, the entire column is sent across the memory bus, but instead in bursts. For DDR4, each burst was 8 (or 16B). With DDR5, it has been increased to as much as 32 (up to 64B). There are two bursts per clock and they happen at the effective data rate.

16n Prefetch: The prefetch has also been scaled up to 16n to keep up with the increased burst length. Like DDR4, there will be two memory-bank arrays per channel connected via a MUX resulting in a higher effective prefetch rate.

Lastly, by adopting a Decision Feedback Equalization (DFE) circuit, which eliminates reflective noise during the channels’ high-speed operation, DDR5 increased the speed per pin considerably.

Feature/OptionDDR4DDR5DDR5 Advantage
Data rates1600-3200 MT/s3200-6400 MT/sIncreases performance and bandwidth
VDD/VDDQ/VPP 1.2/1.2/2.5 1.1/1.1/1.8 Lowers power
Internal VREFVREFDQVREFDQ, VREFCA, VREFCS Improves voltage margins, reduces BOM costs
Device densities  2Gb-16Gb  8Gb-64Gb  Enables larger monolithic devices 
Prefetch  8n 16n  Keeps the internal core clock low
DQ receiver equalization CTLEDFEImproves opening of the received DQ data
 eyes inside the DRAM
Duty cycle adjustment (DCA) None DQS and DQImproves signaling on the transmitted DQ/DQS pins
Internal DQS delay
None DQS interval oscillator Increases robustness against environmental changes 
On-die ECCNone128b+8b SEC, error check and scrub Strengthens on-chip RAS
CRC Write Read/Write  Strengthens system RAS by protecting read data 
Bank groups (BG)/banks 4 BG x 4 banks (x4/x8)
 2 BG x 4 banks (x16)
8 BG x 2 banks (8Gb x4/x8)
 4 BG x 2 banks (8Gb x16)
 8 BG x 4 banks (16-64Gb x4/x8)
 4 BG x 4 banks (16-64Gb x16) 
Improves bandwidth/performance
Command/address interface ODT, CKE, ACT, RAS,
 CAS, WE, A<X:0>
CA<13:0> Dramatically reduces the CA pin count
ODTDQ, DQS, DM/DBI DQ, DQS, DM, CA bus  Improves signal integrity, reduces  BOM costs 
Burst lengthBL8 (and BL4) BL16, BL32 (and BC8 OTF, BL32 OTF) 
Allows 64B cache line fetch with only 1 DIMM subchannel. 
MIR (“mirror” pin) NoneYesImproves DIMM signaling
Bus inversion Data bus inversion (DBI)Command/address inversion (CAI) Reduces VDDQ noise on modules
CA training, CS training None CA training, CS training Improves timing margin on CA and CS pins  
Write leveling training modes YesImprovedCompensates for unmatched DQ-DQS path
Read training patterns Possible with the MPRDedicated MRs for serial (userdefined), clock and LFSR-generated training patternsMakes read timing margin more robust
Mode registers7 x 17 bitsUp to 256 x 8 bits (LPDDR type read/write) 
Provides room to expand
PRECHARGE commands All bank and per bankAll bank, per bank, and same bank PREsb enables precharging-specific bank in each BG
REFRESH commands All bank All bank and same bankREFsb enables refreshing of specific bank in each BG
Loopback modeNone YesEnables testing of the DQ and DQS signaling 

DDR5 also increases the memory density all the way (up) to 64Gb from 16Gb and both the VDD and VPP have gone down to reduce the power draw. Finally, on-chip ECC has also been added and the Mode Registers have also been significantly upgraded. You can see the entire chanage-list in the above table.

Difference Between DDR4 vs GDDR5 vs GDDR6 Memory: DDR4 vs LPDDR4 Comparison; What’s HBM2?

PS: The changes included in this post include the specifications announced by JEDEC, and not just the data provided by SK Hynix.


Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started my first technology blog, Techquila while in college to address my hardware passion. Although largely successful, it was a classic example of too many people trying out multiple different things but getting nothing done. Left in late 2019 and been working on Hardware Times ever since.
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