DDR5 memory has started to become the norm in the PC industry. All newly released processors feature native DDR5 support, with enthusiasts hunting for DDR5-6000, DDR5-6400, and even DDR5-7200 memory kits. With an official JEDEC rating of 4,800Mbps, DDR5 is a massive uplift over DDR4 (3200Mbps). In addition to doubling memory bandwidth, it reduces power consumption and supports on-die ECC (Error Correction).
Several technical upgrades permit this generational uplift, including the doubling of Burst Length (BL), prefetch, and memory banks. Operating modes of preceding DDR4 memory have been retained, allowing the use of smaller four-bank groups and reduced prefetch rates. DDR5 also features fine-grained bank refreshing and DIMMs with two independent channels (dual channel sticks).
Burst Length: DDR4 had a burst rate of 8, the same as DDR3 allowing transfers of up to 16B from the cache at a time. DDR5 increases this to 16, with support for 32-length mode, which allows up to 64-byte cache line fetch with just one DIMM.
To understand what burst length means, you need to know how memory is accessed. When the CPU or cache requests new data, the address is sent to the memory module and then the target memory bank containing the required row, after which the column is located (if not present, a new row is loaded). Keep in mind that there’s a delay after every step.
Then the entire column is sent across the memory bus, but instead in bursts. For DDR4, each burst was 8 (or 16B). With DDR5, it has been increased to 16 with further scope up to 32 (64B). There are two bursts per clock and they happen at the effective data rate.Burst Length
16n Prefetch: DDR5 also scales the prefetch (from 8n on DDR4) to 16n to keep up with the increased burst length. Like DDR4, there are two memory-bank arrays per channel connected via a MUX, resulting in a higher effective prefetch rate (see above image).
Twice as many Bank Groups: DDR5 doubles the total number of memory banks to 32 across 8 bank groups of 4 banks. This boosts the bandwidth and performance as more banks are accessible to the memory controller simultaneously, similar to how dual-rank improves upon single-rank.
Fine-grained bank refreshes: Unlike DDR4, its successor supports individual bank refreshes. With DDR4, memory cells would stall ongoing processes during a refresh. DDR5 allows Same Bank Refresh, which improves the effective bandwidth by allowing some banks to refresh while the rest are still in use.
Dual-channel DIMMs: Similar to its mobile counterpart, DDR5 will feature two 32-bit memory channels per DIMM (versus a single 64-bit on DDR4). This means we’ll start seeing quad-channel configurations with two DIMMs. The two channels per DIMM are independent and can issue commands separately. Since the burst length and prefetch are twice as much as DDR4, this will further improve the overall bandwidth by increasing the total number of data transfers per DIMM.
Integrated voltage regulation: DDR5 reduces VDD and VPP voltages from 1.2v to 1.1v, reducing power consumption. The DRAM voltage regulator has also been moved from the motherboard to the memory modules, reducing circuit complexity for the former.
DDR5 increases the memory density (up) to 64Gb (from 16Gb) while pushing the operating clocks as high as 4200MHz (or 8400MT/s). By adopting a Decision Feedback Equalization (DFE) circuit, which eliminates reflective noise during the channels’ high-speed operation, DDR5 increases the speed per pin considerably.
On-die ECC: The presence of on-die ECC on DDR5 memory has been the subject of many discussions and confusion among consumers and the press. Unlike standard ECC, on-die ECC primarily aims to improve yields at advanced process nodes, allowing cheaper DRAM chips. On-die ECC only detects errors if they take place within a cell or row during refreshes. When the data is moved from the cell to the cache or the CPU, if there’s a bit-flip or data corruption, it won’t be corrected by on-die ECC. Standard ECC corrects data corruption within the cell and as it is moved to another device or an ECC-supported SoC. (Thanks to Ian Cuttress for his explanation)