A few days back. @ExecutableFix on Twitter shared the specs of the top-end Epyc Genoa server processor. Expected to land after Milan, sometime in 2024, these CPUs will leverage TSMC’s 5nm EUV node and the new Zen 4 core microarchitecture. Apart from that, it will also feature a new SP5 socket with 6096 pins (LGA-6096), 12-channel DDR5-5200 memory, and as many as 128 PCIe 5.0 lanes per node.
Although we’re looking at a much more efficient node than Rome and Milan, the increase in compute logic (cores) and the wider memory bus means that the TDP will be a fair bit higher than its 7nm predecessors. The 96-core flagship will have a TDP of 320W, with an adjustable cTDP of 400W for higher boost clocks.
According to a rough estimation by the source, the Epyc Genoa chips are going to be a fair bit larger than Rome and Milan, somewhere in the 20-25% range. Furthermore, the 5nm Zen 4 chiplets seem larger, but also more numerous than the Zen 2/Zen 3 chiplets on Rome/Milan. This indicates that the core count per die/chiplet will remain the same, but as the overall core count has gone up from 64 to 96, the total number of chiplets will increase from 8 to 12. The increase in the per-die size is expected as the core complexity increases (larger FPUs, wider retire Q, etc) and is something we saw upon going from Zen 2 to Zen 3 as well.
Finally, another slide from Chiphell indicates that the Zen 4 core will support AVX-512 which is one of Intel’s only advantages over AMD in the server segment. It’s unclear whether the support will be native with 512-bit wide FPUs or a slower method using multiple 256-bit units, but that’s something we’ll see in time.
The rumor that indicated possible SMT4 support for Genoa seems to have been debunked as the slide mentions that Zen 4 will support only two threads per core.
