Earlier this year, rumors had indicated that AMD’s next-gen Epyc Genoa processors would support AVX512 (512b vector) instructions, robbing Intel of its biggest advantage in the server space. Gigabyte’s leaked documents indicate that this is indeed the case, with some sources even predicting the die size of the large vector registers associated with the new instructions.
This wouldn’t be surprising as AMD has been improving the floating-point capabilities of its Ryzen and Epyc CPUs with every die shrink. Zen and Zen+ (12/14nm) were limited to AVX (128b) with Zen 2 (7nm) adding AVX2 (256-bit) support, Zen 3 further refined it, increasing throughput but the limited die-space prevented the core expansion. With Zen 4 fabbed on TSMC’s 5nm node, there should be enough space to expand the vector units to 512b, thereby allowing AVX512 support. Whether AMD decides to limit this to just the server cores or bring it to the consumer chips as well remains to be seen. AVX512 is known for its high power consumption due to the longer instruction size and longer execution cycles. Therefore, its relevance in the client segment is quite limited.
According to Bits And Chips – Eng, the AVX512 registers on Zen 4 are going to measure 4mm2 (0.5 mm2 per core). Locuza (on Twitter) was quick to do a comparison against the Zen 3 core, and it would seem that the area cost of AVX512 registers is indeed quite severe. (Valium) We’re looking at a 4x increase in the register area with Zen 4 compared to Zen 3, per core (standard 128-bit FP registers are just 0.11mm2 in comparison).
This seems like a rather significant increase in die area just for one particular class of instructions largely limited to the server space. This makes you wonder if AMD will alter the design of the server CCDs to allow AVX512 support or use the same for client chips as well.