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AMD working on Firmware Fix to Improve L3 Cache Performance on Ryzen 5000 CPUs

AMD is working on a firmware (AGESA) update for its newly launched Ryzen 5000 CPUs aimed at improving the L3 cache bandwidth and latency by as much as 25%. The AGESA version 1.2.0.1 will roll out with this patch, following 1.2.0.0 which quashed multiple bugs and improved the overclocking stability, including higher clock speeds for the Infinity Fabric.

Via

As you can see in the above picture (click here to enlarge), for a Ryzen 9 5950X with PBO enabled, the L3 cache bandwidth is roughly 1,200GB/s for reads and 800-850GB/s for writes and copy. Upon overclocking the CPU to 4.5GHz, the same increases to 1,319GB/s and around 1,100GB/s, respectively. That’s an increase of nearly 30% for the L3 write and copy speed, with the read speed improving by ~10%.

With the AGESA version, 1.2.0.1, the same speed can be achieved by simply turning on PBO and increasing the EDC (VRM current peak). With a boost like that, cache-sensitive workloads should see a rather sizable performance boost across the board. The impact, however, will be more noticeable with the Ryzen 9 5900X and 5950X, both of which feature two CCDs and a large L3 cache.

Areej

Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started Techquila while in college to address my hardware passion. Although largely successful, it suffered from many internal weaknesses. Left and now working on Hardware Times, a site purely dedicated to.Processor architectures and in-depth benchmarks. That's what we do here at Hardware Times!
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