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AMD Ryzen Processors w/ Stacked L3 Cache (Up to 96MB) Coming in Late 2021 to Tackle Alder Lake-S

The primary highlight of AMD’s Computex 2021 Keynote was the 3D V-Cache technology that allows the chipmaker to stack a 64 MB L3 cache die on each chiplet for an overall of 192 MB for the full-fledged CPU. Similar to the compute chiplets, the cache (SRAM) die is based on TSMC’s N7 process, bonded using the Through Silicon Vias (TSVs). As per AMD, the cache bandwidth of the added L3 cache crosses the 1 TB/s mark, making it faster (in theory) than the higher-level L1 cache, albeit with higher latency.

AMD CEO, Dr. Lisa Su also demonstrated a prototype on stage that was based on the Zen 3 core architecture with 8-core complexes and 64MB of stacked V-Cache (96MB on CCD; 128MB in total). According to official benchmarks, this sample was 15-20% faster than a standard Ryzen 5000 processor with the same core and clock specs.

The SKU w/ 3D V-Cache was 25% faster than a 12-core Ryzen 9 5900X

In terms of specifications, the cache die is slightly thinner than the base die, and as such, additional silicon layers are used on both ends to provide structural integrity and stability. At the same time, the dies are also thinner in order to retain the same substrate and heat-spreader as the vanilla Ryzen 5000 lineup.

The use of 3D V-Cache increases the interconnect density by 200x compared to traditional 2D packaging while also increasing efficiency by up to 3x. Considering that the technology is fabbed by TSMC and uses a TSV interface, we’re likely looking at a derivative of TSMC’s Chip-on-Wafer technology.

As per info received by Dr. Ian Cutress, AMD is working on Zen 3-based Ryzen 5000 processors leveraging 3D V-Cache for a late 2021/early 2022 release, likely as a competitor to Intel’s much-anticipated Alder Lake-S lineup. Considering the near-zero performance delta between Rocket Lake-S and Ryzen 5000, it’s very likely that AMD will be retaining the lead in gaming performance at the very least (plus multi-core performance).

Update: As per AMD, the stacked L3 cache will be seen by the processor as part of the existing L3 cache, with similar latencies. In addition, they can be turned off when idle for efficiency reasons. 

Areej

Computer Engineering dropout (3 years), writer, journalist, and amateur poet. I started my first technology blog, Techquila while in college to address my hardware passion. Although largely successful, it was a classic example of too many people trying out multiple different things but getting nothing done. Left in late 2019 and been working on Hardware Times ever since.
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